tests/asicworld/code_tidbits_fsm_using_function.v

   1 //-----------------------------------------------------
   2 // This is FSM demo program using function
   3 // Design Name : fsm_using_function
   4 // File Name   : fsm_using_function.v
   5 //-----------------------------------------------------
   6 module fsm_using_function (
   7 clock      , // clock
   8 reset      , // Active high, syn reset
   9 req_0      , // Request 0
  10 req_1      , // Request 1
  11 gnt_0      , // Grant 0
  12 gnt_1
  13 );
  14 //-------------Input Ports-----------------------------
  15 input   clock,reset,req_0,req_1;
  16  //-------------Output Ports----------------------------
  17 output  gnt_0,gnt_1;
  18 //-------------Input ports Data Type-------------------
  19 wire    clock,reset,req_0,req_1;
  20 //-------------Output Ports Data Type------------------
  21 reg     gnt_0,gnt_1;
  22 //-------------Internal Constants--------------------------
  23 parameter SIZE = 3           ;
  24 parameter IDLE  = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100 ;
  25 //-------------Internal Variables---------------------------
  26 reg   [SIZE-1:0]          state        ;// Seq part of the FSM
  27 wire  [SIZE-1:0]          next_state   ;// combo part of FSM
  28 //----------Code startes Here------------------------
  29 assign next_state = fsm_function(state, req_0, req_1);
  30 //----------Function for Combo Logic-----------------
  31 function [SIZE-1:0] fsm_function;
  32   input  [SIZE-1:0]  state ;
  33   input    req_0 ;
  34   input    req_1 ;
  35   case(state)
  36    IDLE : if (req_0 == 1'b1) begin
  37                 fsm_function = GNT0;
  38               end else if (req_1 == 1'b1) begin
  39                 fsm_function= GNT1;
  40               end else begin
  41                 fsm_function = IDLE;
  42               end
  43    GNT0 : if (req_0 == 1'b1) begin
  44                 fsm_function = GNT0;
  45               end else begin
  46                 fsm_function = IDLE;
  47               end
  48    GNT1 : if (req_1 == 1'b1) begin
  49                 fsm_function = GNT1;
  50           end else begin
  51                 fsm_function = IDLE;
  52               end
  53    default : fsm_function = IDLE;
  54   endcase
  55 endfunction
  56 //----------Seq Logic-----------------------------
  57 always @ (posedge clock)
  58 begin : FSM_SEQ
  59   if (reset == 1'b1) begin
  60     state <= #1 IDLE;
  61   end else begin
  62     state <= #1 next_state;
  63   end
  64 end
  65 //----------Output Logic-----------------------------
  66 always @ (posedge clock)
  67 begin : OUTPUT_LOGIC
  68 if (reset == 1'b1) begin
  69   gnt_0 <= #1 1'b0;
  70   gnt_1 <= #1 1'b0;
  71 end
  72 else begin
  73   case(state)
  74     IDLE : begin
  75                   gnt_0 <= #1 1'b0;
  76                   gnt_1 <= #1 1'b0;
  77                end
  78    GNT0 : begin
  79                    gnt_0 <= #1 1'b1;
  80                    gnt_1 <= #1 1'b0;
  81                 end
  82    GNT1 : begin
  83                    gnt_0 <= #1 1'b0;
  84                    gnt_1 <= #1 1'b1;
  85                 end
  86    default : begin
  87                     gnt_0 <= #1 1'b0;
  88                     gnt_1 <= #1 1'b0;
  89                   end
  90   endcase
  91 end
  92 end // End Of Block OUTPUT_LOGIC
  93
  94 endmodule // End of Module arbiter