tests/asicworld/code_tidbits_fsm_using_single_always.v

   1 //====================================================
   2 // This is FSM demo program using single always
   3 // for both seq and combo logic
   4 // Design Name : fsm_using_single_always
   5 // File Name   : fsm_using_single_always.v
   6 //=====================================================
   7 module fsm_using_single_always (
   8 clock      , // clock
   9 reset      , // Active high, syn reset
  10 req_0      , // Request 0
  11 req_1      , // Request 1
  12 gnt_0      , // Grant 0
  13 gnt_1
  14 );
  15 //=============Input Ports=============================
  16 input   clock,reset,req_0,req_1;
  17  //=============Output Ports===========================
  18 output  gnt_0,gnt_1;
  19 //=============Input ports Data Type===================
  20 wire    clock,reset,req_0,req_1;
  21 //=============Output Ports Data Type==================
  22 reg     gnt_0,gnt_1;
  23 //=============Internal Constants======================
  24 parameter SIZE = 3           ;
  25 parameter IDLE  = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100 ;
  26 //=============Internal Variables======================
  27 reg   [SIZE-1:0]          state        ;// Seq part of the FSM
  28 reg   [SIZE-1:0]          next_state   ;// combo part of FSM
  29 //==========Code startes Here==========================
  30 always @ (posedge clock)
  31 begin : FSM
  32 if (reset == 1'b1) begin
  33   state <= #1 IDLE;
  34   gnt_0 <= 0;
  35   gnt_1 <= 0;
  36 end else
  37  case(state)
  38    IDLE : if (req_0 == 1'b1) begin
  39                 state <= #1 GNT0;
  40                 gnt_0 <= 1;
  41               end else if (req_1 == 1'b1) begin
  42                 gnt_1 <= 1;
  43                 state <= #1 GNT1;
  44               end else begin
  45                 state <= #1 IDLE;
  46               end
  47    GNT0 : if (req_0 == 1'b1) begin
  48                 state <= #1 GNT0;
  49               end else begin
  50                 gnt_0 <= 0;
  51                 state <= #1 IDLE;
  52               end
  53    GNT1 : if (req_1 == 1'b1) begin
  54                 state <= #1 GNT1;
  55               end else begin
  56                 gnt_1 <= 0;
  57                 state <= #1 IDLE;
  58               end
  59    default : state <= #1 IDLE;
  60 endcase
  61 end
  62
  63 endmodule // End of Module arbiter