1 //====================================================
2 // This is FSM demo program using single always
3 // for both seq and combo logic
4 // Design Name : fsm_using_single_always
5 // File Name : fsm_using_single_always.v
6 //=====================================================
7 module fsm_using_single_always (
9 reset , // Active high, syn reset
15 //=============Input Ports=============================
16 input clock,reset,req_0,req_1;
17 //=============Output Ports===========================
19 //=============Input ports Data Type===================
20 wire clock,reset,req_0,req_1;
21 //=============Output Ports Data Type==================
23 //=============Internal Constants======================
25 parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100 ;
26 //=============Internal Variables======================
27 reg [SIZE-1:0] state ;// Seq part of the FSM
28 reg [SIZE-1:0] next_state ;// combo part of FSM
29 //==========Code startes Here==========================
30 always @ (posedge clock)
32 if (reset == 1'b1) begin
38 IDLE : if (req_0 == 1'b1) begin
41 end else if (req_1 == 1'b1) begin
47 GNT0 : if (req_0 == 1'b1) begin
53 GNT1 : if (req_1 == 1'b1) begin
59 default : state <= #1 IDLE;
63 endmodule // End of Module arbiter