tests/asicworld/code_tidbits_reg_seq_example.v

   1 module reg_seq_example( clk, reset, d, q);
   2 input clk, reset, d;
   3 output q;
   4
   5 reg   q;
   6 wire clk, reset, d;
   7
   8 always @ (posedge clk or posedge reset)
   9 if (reset) begin
  10   q <= 1'b0;
  11 end else begin
  12   q <= d;
  13 end
  14
  15 endmodule