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HEAD
Merge pull request #1073 from whitequark/ecp5-diamond-iob
[yosys.git]
/
tests
/
asicworld
/
code_tidbits_wire_example.v
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module wire_example( a, b, y);
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input a, b;
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output y;
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wire a, b, y;
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assign y = a & b;
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endmodule