tests/asicworld/code_verilog_tutorial_addbit.v

   1 module addbit (
   2 a      , // first input
   3 b      , // Second input
   4 ci     , // Carry input
   5 sum    , // sum output
   6 co       // carry output
   7 );
   8 //Input declaration
   9 input a;
  10 input b;
  11 input ci;
  12 //Ouput declaration
  13 output sum;
  14 output co;
  15 //Port Data types
  16 wire  a;
  17 wire  b;
  18 wire  ci;
  19 wire  sum;
  20 wire  co;
  21 //Code starts here
  22 assign {co,sum} = a + b + ci;
  23
  24 endmodule // End of Module addbit