tests/asicworld/code_verilog_tutorial_always_example.v

   1 module always_example();
   2 reg clk,reset,enable,q_in,data;
   3
   4 always @ (posedge clk)
   5 if (reset)  begin
   6    data <= 0;
   7 end else if (enable) begin
   8    data <= q_in;
   9 end
  10
  11 endmodule