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Add #1460 testcase
[yosys.git]
/
tests
/
asicworld
/
code_verilog_tutorial_bus_con.v
1
module bus_con (a,b, y);
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input [3:0] a, b;
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output [7:0] y;
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wire [7:0] y;
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assign y = {a,b};
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endmodule