projects
/
yosys.git
/ blob
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
history
|
raw
|
HEAD
Add a couple more tests
[yosys.git]
/
tests
/
asicworld
/
code_verilog_tutorial_bus_con.v
1
module bus_con (a,b, y);
2
input [3:0] a, b;
3
output [7:0] y;
4
wire [7:0] y;
5
6
assign y = {a,b};
7
8
endmodule