tests/asicworld/code_verilog_tutorial_comment.v

   1 /* This is a
   2   Multi line comment
   3   example */
   4 module addbit (
   5 a,
   6 b,
   7 ci,
   8 sum,
   9 co);
  10
  11 // Input Ports  Single line comment
  12 input           a;
  13 input           b;
  14 input           ci;
  15 // Output ports
  16 output         sum;
  17 output         co;
  18 // Data Types
  19 wire            a;
  20 wire            b;
  21 wire            ci;
  22 wire            sum;
  23 wire            co;
  24
  25 endmodule