tests/asicworld/code_verilog_tutorial_counter.v

   1 //-----------------------------------------------------
   2 // Design Name : counter
   3 // File Name   : counter.v
   4 // Function    : 4 bit up counter
   5 // Coder       : Deepak
   6 //-----------------------------------------------------
   7 module counter (clk, reset, enable, count);
   8 input clk, reset, enable;
   9 output [3:0] count;
  10 reg [3:0] count;
  11
  12 always @ (posedge clk)
  13 if (reset == 1'b1) begin
  14   count <= 0;
  15 end else if ( enable == 1'b1) begin
  16   count <= count + 1;
  17 end
  18
  19 endmodule