tests/asicworld/code_verilog_tutorial_counter_tb.v

   1 ///////////////////////////////////////////////////////////////////////////
   2 // MODULE               : counter_tb                                     //
   3 // TOP MODULE           : --                                             //
   4 //                                                                       //
   5 // PURPOSE              : 4-bit up counter test bench                    //
   6 //                                                                       //
   7 // DESIGNER             : Deepak Kumar Tala                              //
   8 //                                                                       //
   9 // Revision History                                                      //
  10 //                                                                       //
  11 // DEVELOPMENT HISTORY  :                                                //
  12 //               Rev0.0 : Jan 03, 2003                                   //
  13 //                        Initial Revision                               //
  14 //                                                                       //
  15 ///////////////////////////////////////////////////////////////////////////
  16 module testbench;
  17
  18 integer file;
  19 reg clk = 0, reset = 0, enable = 0;
  20 wire [3:0] count;
  21 reg dut_error = 0;
  22
  23 counter U0 (
  24 .clk    (clk),
  25 .reset  (reset),
  26 .enable (enable),
  27 .count  (count)
  28 );
  29
  30 event reset_enable;
  31 event terminate_sim;
  32
  33 initial
  34  file = $fopen(`outfile);
  35
  36 always
  37   #5 clk = !clk;
  38
  39 initial
  40 @ (terminate_sim)  begin
  41  $fdisplay (file, "Terminating simulation");
  42  if (dut_error == 0) begin
  43    $fdisplay (file, "Simulation Result : PASSED");
  44  end
  45  else begin
  46    $fdisplay (file, "Simulation Result : FAILED");
  47  end
  48  $fdisplay (file, "###################################################");
  49  #1 $finish;
  50 end
  51
  52
  53
  54 event reset_done;
  55
  56 initial
  57 forever begin
  58  @ (reset_enable);
  59  @ (negedge clk)
  60  $fdisplay (file, "Applying reset");
  61    reset = 1;
  62  @ (negedge clk)
  63    reset = 0;
  64  $fdisplay (file, "Came out of Reset");
  65  -> reset_done;
  66 end
  67
  68 initial begin
  69   #10 -> reset_enable;
  70   @ (reset_done);
  71   @ (negedge clk);
  72   enable = 1;
  73   repeat (5)
  74   begin
  75    @ (negedge clk);
  76   end
  77   enable = 0;
  78   #5 -> terminate_sim;
  79 end
  80
  81
  82 reg [3:0] count_compare;
  83
  84 always @ (posedge clk)
  85 if (reset == 1'b1)
  86  count_compare <= 0;
  87 else if ( enable == 1'b1)
  88  count_compare <= count_compare + 1;
  89
  90
  91
  92 always @ (negedge clk)
  93 if (count_compare != count) begin
  94   $fdisplay (file, "DUT ERROR AT TIME%d",$time);
  95   $fdisplay (file, "Expected value %d, Got Value %d", count_compare, count);
  96   dut_error = 1;
  97   #5 -> terminate_sim;
  98 end
  99
 100 endmodule
 101