1 ///////////////////////////////////////////////////////////////////////////
2 // MODULE : counter_tb //
5 // PURPOSE : 4-bit up counter test bench //
7 // DESIGNER : Deepak Kumar Tala //
11 // DEVELOPMENT HISTORY : //
12 // Rev0.0 : Jan 03, 2003 //
13 // Initial Revision //
15 ///////////////////////////////////////////////////////////////////////////
18 reg clk, reset, enable;
34 $display ("###################################################");
46 $dumpfile ("counter.vcd");
52 @ (terminate_sim) begin
53 $display ("Terminating simulation");
54 if (dut_error == 0) begin
55 $display ("Simulation Result : PASSED");
58 $display ("Simulation Result : FAILED");
60 $display ("###################################################");
72 $display ("Applying reset");
76 $display ("Came out of Reset");
94 reg [3:0] count_compare;
96 always @ (posedge clk)
99 else if ( enable == 1'b1)
100 count_compare <= count_compare + 1;
104 always @ (negedge clk)
105 if (count_compare != count) begin
106 $display ("DUT ERROR AT TIME%d",$time);
107 $display ("Expected value %d, Got Value %d", count_compare, count);