tests/asicworld/code_verilog_tutorial_counter_tb.v

   1 ///////////////////////////////////////////////////////////////////////////
   2 // MODULE               : counter_tb                                     //
   3 // TOP MODULE           : --                                             //
   4 //                                                                       //
   5 // PURPOSE              : 4-bit up counter test bench                    //
   6 //                                                                       //
   7 // DESIGNER             : Deepak Kumar Tala                              //
   8 //                                                                       //
   9 // Revision History                                                      //
  10 //                                                                       //
  11 // DEVELOPMENT HISTORY  :                                                //
  12 //               Rev0.0 : Jan 03, 2003                                   //
  13 //                        Initial Revision                               //
  14 //                                                                       //
  15 ///////////////////////////////////////////////////////////////////////////
  16 module testbench;
  17
  18 reg clk, reset, enable;
  19 wire [3:0] count;
  20 reg dut_error;
  21
  22 counter U0 (
  23 .clk    (clk),
  24 .reset  (reset),
  25 .enable (enable),
  26 .count  (count)
  27 );
  28
  29 event reset_enable;
  30 event terminate_sim;
  31
  32 initial
  33 begin
  34  $display ("###################################################");
  35  clk = 0;
  36  reset = 0;
  37  enable = 0;
  38  dut_error = 0;
  39 end
  40
  41 always
  42   #5 clk = !clk;
  43
  44 initial
  45 begin
  46   $dumpfile ("counter.vcd");
  47   $dumpvars;
  48 end
  49
  50
  51 initial
  52 @ (terminate_sim)  begin
  53  $display ("Terminating simulation");
  54  if (dut_error == 0) begin
  55    $display ("Simulation Result : PASSED");
  56  end
  57  else begin
  58    $display ("Simulation Result : FAILED");
  59  end
  60  $display ("###################################################");
  61  #1 $finish;
  62 end
  63
  64
  65
  66 event reset_done;
  67
  68 initial
  69 forever begin
  70  @ (reset_enable);
  71  @ (negedge clk)
  72  $display ("Applying reset");
  73    reset = 1;
  74  @ (negedge clk)
  75    reset = 0;
  76  $display ("Came out of Reset");
  77  -> reset_done;
  78 end
  79
  80 initial begin
  81   #10 -> reset_enable;
  82   @ (reset_done);
  83   @ (negedge clk);
  84   enable = 1;
  85   repeat (5)
  86   begin
  87    @ (negedge clk);
  88   end
  89   enable = 0;
  90   #5 -> terminate_sim;
  91 end
  92
  93
  94 reg [3:0] count_compare;
  95
  96 always @ (posedge clk)
  97 if (reset == 1'b1)
  98  count_compare <= 0;
  99 else if ( enable == 1'b1)
 100  count_compare <= count_compare + 1;
 101
 102
 103
 104 always @ (negedge clk)
 105 if (count_compare != count) begin
 106   $display ("DUT ERROR AT TIME%d",$time);
 107   $display ("Expected value %d, Got Value %d", count_compare, count);
 108   dut_error = 1;
 109   #5 -> terminate_sim;
 110 end
 111
 112 endmodule
 113