1 ///////////////////////////////////////////////////////////////////////////
2 // MODULE : counter_tb //
5 // PURPOSE : 4-bit up counter test bench //
7 // DESIGNER : Deepak Kumar Tala //
11 // DEVELOPMENT HISTORY : //
12 // Rev0.0 : Jan 03, 2003 //
13 // Initial Revision //
15 ///////////////////////////////////////////////////////////////////////////
19 reg clk = 0, reset = 0, enable = 0;
34 file = $fopen(`outfile);
40 @ (terminate_sim) begin
41 $fdisplay (file, "Terminating simulation");
42 if (dut_error == 0) begin
43 $fdisplay (file, "Simulation Result : PASSED");
46 $fdisplay (file, "Simulation Result : FAILED");
48 $fdisplay (file, "###################################################");
60 $fdisplay (file, "Applying reset");
64 $fdisplay (file, "Came out of Reset");
82 reg [3:0] count_compare;
84 always @ (posedge clk)
87 else if ( enable == 1'b1)
88 count_compare <= count_compare + 1;
92 always @ (negedge clk)
93 if (count_compare != count) begin
94 $fdisplay (file, "DUT ERROR AT TIME%d",$time);
95 $fdisplay (file, "Expected value %d, Got Value %d", count_compare, count);