tests/asicworld/code_verilog_tutorial_d_ff.v

   1 // D flip-flop Code
   2 module d_ff ( d, clk, q, q_bar);
   3 input d ,clk;
   4 output q, q_bar;
   5 wire d ,clk;
   6 reg q, q_bar;
   7
   8 always @ (posedge clk)
   9 begin
  10   q <= d;
  11   q_bar <= !d;
  12 end
  13
  14 endmodule