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Merge remote-tracking branch 'origin/master' into xc7mux
[yosys.git]
/
tests
/
asicworld
/
code_verilog_tutorial_d_ff.v
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// D flip-flop Code
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module d_ff ( d, clk, q, q_bar);
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input d ,clk;
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output q, q_bar;
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wire d ,clk;
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reg q, q_bar;
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always @ (posedge clk)
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begin
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q <= d;
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q_bar <= !d;
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end
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endmodule