tests/asicworld/code_verilog_tutorial_decoder.v

   1 module decoder (in,out);
   2 input [2:0] in;
   3 output [7:0] out;
   4 wire [7:0] out;
   5 assign out  =   (in == 3'b000 ) ? 8'b0000_0001 :
   6 (in == 3'b001 ) ? 8'b0000_0010 :
   7 (in == 3'b010 ) ? 8'b0000_0100 :
   8 (in == 3'b011 ) ? 8'b0000_1000 :
   9 (in == 3'b100 ) ? 8'b0001_0000 :
  10 (in == 3'b101 ) ? 8'b0010_0000 :
  11 (in == 3'b110 ) ? 8'b0100_0000 :
  12 (in == 3'b111 ) ? 8'b1000_0000 : 8'h00;
  13
  14 endmodule