tests/asicworld/code_verilog_tutorial_decoder_always.v

   1 module decoder_always (in,out);
   2 input [2:0] in;
   3 output [7:0] out;
   4 reg [7:0] out;
   5
   6 always @ (in)
   7 begin
   8   out = 0;
   9   case (in)
  10     3'b001 : out = 8'b0000_0001;
  11     3'b010 : out = 8'b0000_0010;
  12     3'b011 : out = 8'b0000_0100;
  13     3'b100 : out = 8'b0000_1000;
  14     3'b101 : out = 8'b0001_0000;
  15     3'b110 : out = 8'b0100_0000;
  16     3'b111 : out = 8'b1000_0000;
  17   endcase
  18 end
  19
  20 endmodule