tests/asicworld/code_verilog_tutorial_escape_id.v

   1 // There must be white space after the
   2 // string which uses escape character
   3 module \1dff (
   4 q,      // Q output
   5 \q~ ,   // Q_out output
   6 d,      // D input
   7 cl$k,   // CLOCK input
   8 \reset* // Reset input
   9 );
  10
  11 input d, cl$k, \reset* ;
  12 output q, \q~ ;
  13
  14 endmodule