tests/asicworld/code_verilog_tutorial_explicit.v

   1 module explicit();
   2 reg clk,d,rst,pre;
   3 wire q;
   4
   5 // Here q_bar is not connected
   6 // We can connect ports in any order
   7 dff u0 (
   8 .q      (q),
   9 .d      (d),
  10 .clk    (clk),
  11 .q_bar  (),
  12 .rst    (rst),
  13 .pre    (pre)
  14 );
  15
  16 endmodule
  17
  18 // D fli-flop
  19 module dff (q, q_bar, clk, d, rst, pre);
  20 input clk, d, rst, pre;
  21 output q, q_bar;
  22 reg q;
  23
  24 assign q_bar = ~q;
  25
  26 always @ (posedge clk)
  27 if (rst == 1'b1) begin
  28   q <= 0;
  29 end else if (pre == 1'b1) begin
  30   q <= 1;
  31 end else begin
  32   q <= d;
  33 end
  34
  35 endmodule