1 //-----------------------------------------------------
2 // This is my second Verilog Design
3 // Design Name : first_counter
4 // File Name : first_counter.v
5 // Function : This is a 4 bit up-counter with
6 // Synchronous active high reset and
7 // with active high enable signal
8 //-----------------------------------------------------
10 clock , // Clock input of the design
11 reset , // active high, synchronous Reset input
12 enable , // Active high enable signal for counter
13 counter_out // 4 bit vector output of the counter
14 ); // End of port list
15 //-------------Input Ports-----------------------------
19 //-------------Output Ports----------------------------
20 output [3:0] counter_out ;
21 //-------------Input ports Data Type-------------------
22 // By rule all the input ports should be wires
26 //-------------Output Ports Data Type------------------
27 // Output port can be a storage element (reg) or a wire
28 reg [3:0] counter_out ;
30 //------------Code Starts Here-------------------------
31 // Since this counter is a positive edge trigged one,
32 // We trigger the below block with respect to positive
34 always @ (posedge clock)
35 begin : COUNTER // Block Name
36 // At every rising edge of clock we check if reset is active
37 // If active, we load the counter output with 4'b0000
38 if (reset == 1'b1) begin
39 counter_out <= 4'b0000;
41 // If enable is active, then we increment the counter
42 else if (enable == 1'b1) begin
43 counter_out <= counter_out + 1;
45 end // End of Block COUNTER
47 endmodule // End of Module counter