tests/asicworld/code_verilog_tutorial_first_counter_tb.v

   1 module testbench();
   2 // Declare inputs as regs and outputs as wires
   3 reg clock = 1, reset = 0, enable = 0;
   4 wire [3:0] counter_out;
   5 integer file;
   6
   7 // Initialize all variables
   8 initial begin
   9   file = $fopen(`outfile);
  10   $fdisplay (file, "time\t clk reset enable counter");
  11   #5 reset = 1;    // Assert the reset
  12   #10 reset = 0;   // De-assert the reset
  13   #10 enable = 1;  // Assert enable
  14   #100 enable = 0; // De-assert enable
  15   #5 $finish;      // Terminate simulation
  16 end
  17
  18 always @(negedge clock)
  19   $fdisplay (file, "%g\t %b   %b     %b      %b",
  20           $time, clock, reset, enable, counter_out);
  21
  22 // Clock generator
  23 initial begin
  24   #1;
  25   forever
  26     #5 clock = ~clock; // Toggle clock every 5 ticks
  27 end
  28
  29 // Connect DUT to test bench
  30 first_counter U_counter (
  31 clock,
  32 reset,
  33 enable,
  34 counter_out
  35 );
  36
  37 endmodule