tests/asicworld/code_verilog_tutorial_flip_flop.v

   1 module flif_flop (clk,reset, q, d);
   2 input clk, reset, d;
   3 output q;
   4 reg q;
   5
   6 always @ (posedge clk )
   7 begin
   8   if (reset == 1) begin
   9     q <= 0;
  10   end else begin
  11     q <= d;
  12   end
  13 end
  14
  15 endmodule