tests/asicworld/code_verilog_tutorial_fsm_full.v

   1 module fsm_full(
   2 clock , // Clock
   3 reset , // Active high reset
   4 req_0 , // Active high request from agent 0
   5 req_1 , // Active high request from agent 1
   6 req_2 , // Active high request from agent 2
   7 req_3 , // Active high request from agent 3
   8 gnt_0 , // Active high grant to agent 0
   9 gnt_1 , // Active high grant to agent 1
  10 gnt_2 , // Active high grant to agent 2
  11 gnt_3   // Active high grant to agent 3
  12 );
  13 // Port declaration here
  14 input clock ; // Clock
  15 input reset ; // Active high reset
  16 input req_0 ; // Active high request from agent 0
  17 input req_1 ; // Active high request from agent 1
  18 input req_2 ; // Active high request from agent 2
  19 input req_3 ; // Active high request from agent 3
  20 output gnt_0 ; // Active high grant to agent 0
  21 output gnt_1 ; // Active high grant to agent 1
  22 output gnt_2 ; // Active high grant to agent 2
  23 output gnt_3 ; // Active high grant to agent
  24
  25 // Internal Variables
  26 reg    gnt_0 ; // Active high grant to agent 0
  27 reg    gnt_1 ; // Active high grant to agent 1
  28 reg    gnt_2 ; // Active high grant to agent 2
  29 reg    gnt_3 ; // Active high grant to agent
  30
  31 parameter  [2:0]  IDLE  = 3'b000;
  32 parameter  [2:0]  GNT0  = 3'b001;
  33 parameter  [2:0]  GNT1  = 3'b010;
  34 parameter  [2:0]  GNT2  = 3'b011;
  35 parameter  [2:0]  GNT3  = 3'b100;
  36
  37 reg [2:0] state, next_state;
  38
  39 always @ (state or req_0 or req_1 or req_2 or req_3)
  40 begin
  41   next_state = 0;
  42   case(state)
  43     IDLE : if (req_0 == 1'b1) begin
  44              next_state = GNT0;
  45            end else if (req_1 == 1'b1) begin
  46              next_state= GNT1;
  47            end else if (req_2 == 1'b1) begin
  48              next_state= GNT2;
  49            end else if (req_3 == 1'b1) begin
  50              next_state= GNT3;
  51            end else begin
  52              next_state = IDLE;
  53            end
  54     GNT0 : if (req_0 == 1'b0) begin
  55              next_state = IDLE;
  56            end else begin
  57              next_state = GNT0;
  58           end
  59     GNT1 : if (req_1 == 1'b0) begin
  60              next_state = IDLE;
  61            end else begin
  62              next_state = GNT1;
  63           end
  64     GNT2 : if (req_2 == 1'b0) begin
  65              next_state = IDLE;
  66            end else begin
  67              next_state = GNT2;
  68           end
  69     GNT3 : if (req_3 == 1'b0) begin
  70              next_state = IDLE;
  71            end else begin
  72              next_state = GNT3;
  73           end
  74    default : next_state = IDLE;
  75   endcase
  76 end
  77
  78 always @ (posedge clock)
  79 begin : OUTPUT_LOGIC
  80   if (reset) begin
  81     gnt_0 <= 1'b0;
  82     gnt_1 <= 1'b0;
  83     gnt_2 <= 1'b0;
  84     gnt_3 <= 1'b0;
  85     state <= IDLE;
  86   end else begin
  87     state <= next_state;
  88     case(state)
  89         IDLE : begin
  90                 gnt_0 <= 1'b0;
  91                 gnt_1 <= 1'b0;
  92                 gnt_2 <= 1'b0;
  93                 gnt_3 <= 1'b0;
  94                end
  95         GNT0 : begin
  96                  gnt_0 <= 1'b1;
  97                end
  98         GNT1 : begin
  99                  gnt_1 <= 1'b1;
 100                end
 101         GNT2 : begin
 102                  gnt_2 <= 1'b1;
 103                end
 104         GNT3 : begin
 105                  gnt_3 <= 1'b1;
 106                end
 107      default : begin
 108                  state <= IDLE;
 109                end
 110     endcase
 111   end
 112 end
 113
 114 endmodule