2 reg clock = 0 , reset ;
3 reg req_0 , req_1 , req_2 , req_3;
4 wire gnt_0 , gnt_1 , gnt_2 , gnt_3 ;
8 // $dumpfile("testbench.vcd");
9 // $dumpvars(0, testbench);
10 file = $fopen(`outfile);
11 $fdisplay(file, "Time\t R0 R1 R2 R3 G0 G1 G2 G3");
31 always @(negedge clock)
32 $fdisplay(file, "%g\t %b %b %b %b %b %b %b %b",
33 $time, req_0, req_1, req_2, req_3, gnt_0, gnt_1, gnt_2, gnt_3);
43 reset , // Active high reset
44 req_0 , // Active high request from agent 0
45 req_1 , // Active high request from agent 1
46 req_2 , // Active high request from agent 2
47 req_3 , // Active high request from agent 3
48 gnt_0 , // Active high grant to agent 0
49 gnt_1 , // Active high grant to agent 1
50 gnt_2 , // Active high grant to agent 2
51 gnt_3 // Active high grant to agent 3