tests/asicworld/code_verilog_tutorial_fsm_full_tb.v

   1 module testbench();
   2 reg clock = 0 , reset ;
   3 reg req_0 , req_1 ,  req_2 , req_3;
   4 wire gnt_0 , gnt_1 , gnt_2 , gnt_3 ;
   5 integer file;
   6
   7 initial begin
   8   // $dumpfile("testbench.vcd");
   9   // $dumpvars(0, testbench);
  10   file = $fopen(`outfile);
  11   $fdisplay(file, "Time\t    R0 R1 R2 R3 G0 G1 G2 G3");
  12   clock = 0;
  13   reset = 1;
  14   req_0 = 0;
  15   req_1 = 0;
  16   req_2 = 0;
  17   req_3 = 0;
  18   #10 reset = 1;
  19   #10 reset = 0;
  20   #10 req_0 = 1;
  21   #20 req_0 = 0;
  22   #10 req_1 = 1;
  23   #20 req_1 = 0;
  24   #10 req_2 = 1;
  25   #20 req_2 = 0;
  26   #10 req_3 = 1;
  27   #20 req_3 = 0;
  28   #10 $finish;
  29 end
  30
  31 always @(negedge clock)
  32   $fdisplay(file, "%g\t    %b  %b  %b  %b  %b  %b  %b  %b",
  33     $time, req_0, req_1, req_2, req_3, gnt_0, gnt_1, gnt_2, gnt_3);
  34
  35 initial begin
  36  #1;
  37  forever
  38    #2 clock = ~clock;
  39 end
  40
  41 fsm_full U_fsm_full(
  42 clock , // Clock
  43 reset , // Active high reset
  44 req_0 , // Active high request from agent 0
  45 req_1 , // Active high request from agent 1
  46 req_2 , // Active high request from agent 2
  47 req_3 , // Active high request from agent 3
  48 gnt_0 , // Active high grant to agent 0
  49 gnt_1 , // Active high grant to agent 1
  50 gnt_2 , // Active high grant to agent 2
  51 gnt_3   // Active high grant to agent 3
  52 );
  53
  54 endmodule