tests/asicworld/code_verilog_tutorial_good_code.v

   1       module addbit (
   2       a,
   3       b,
   4       ci,
   5       sum,
   6       co);
   7       input           a;
   8       input           b;
   9       input           ci;
  10       output         sum;
  11       output         co;
  12       wire            a;
  13       wire            b;
  14       wire            ci;
  15       wire            sum;
  16       wire            co;
  17
  18       endmodule