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Merge remote-tracking branch 'origin/master' into xc7mux
[yosys.git]
/
tests
/
asicworld
/
code_verilog_tutorial_good_code.v
1
module addbit (
2
a,
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b,
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ci,
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sum,
6
co);
7
input a;
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input b;
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input ci;
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output sum;
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output co;
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wire a;
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wire b;
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wire ci;
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wire sum;
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wire co;
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18
endmodule