tests/asicworld/code_verilog_tutorial_if_else.v

   1 module if_else();
   2
   3 reg dff;
   4 wire clk,din,reset;
   5
   6 always @ (posedge clk)
   7 if (reset) begin
   8   dff <= 0;
   9 end else  begin
  10   dff <= din;
  11 end
  12
  13 endmodule