tests/asicworld/code_verilog_tutorial_mux_21.v

   1 module mux_21 (a,b,sel,y);
   2                 input a, b;
   3                 output y;
   4                 input sel;
   5                 wire y;
   6
   7                 assign y = (sel) ? b : a;
   8
   9 endmodule