tests/asicworld/code_verilog_tutorial_n_out_primitive.v

   1 module n_out_primitive();
   2
   3 wire out,out_0,out_1,out_2,out_3,out_a,out_b,out_c;
   4 wire in;
   5
   6 // one output Buffer gate
   7 buf u_buf0 (out,in);
   8 // four output Buffer gate
   9 buf u_buf1 (out_0, out_1, out_2, out_3, in);
  10 // three output Invertor gate
  11 not u_not0 (out_a, out_b, out_c, in);
  12
  13 endmodule