tests/asicworld/code_verilog_tutorial_parity.v

   1 //-----------------------------------------------------
   2 // This is simple parity Program
   3 // Design Name : parity
   4 // File Name   : parity.v
   5 // Function    : This program shows how a verilog
   6 //               primitive/module port connection are done
   7 // Coder       : Deepak
   8 //-----------------------------------------------------
   9 module parity (
  10 a      , // First input
  11 b      , // Second input
  12 c      , // Third Input
  13 d      , // Fourth Input
  14 y        // Parity  output
  15 );
  16
  17 // Input Declaration
  18 input       a       ;
  19 input       b       ;
  20 input       c       ;
  21 input       d       ;
  22 // Ouput Declaration
  23 output      y      ;
  24 // port data types
  25 wire        a        ;
  26 wire        b        ;
  27 wire        c        ;
  28 wire        d        ;
  29 wire        y        ;
  30 // Internal variables
  31 wire        out_0 ;
  32 wire        out_1 ;
  33
  34 // Code starts Here
  35 xor u0 (out_0,a,b);
  36
  37 xor u1 (out_1,c,d);
  38
  39 xor u2 (y,out_0,out_1);
  40
  41 endmodule // End Of Module parity