Merge pull request #1143 from YosysHQ/clifford/fix1135
[yosys.git] / tests / asicworld / code_verilog_tutorial_simple_function.v
1 module simple_function();
2
3 function myfunction;
4 input a, b, c, d;
5 begin
6 myfunction = ((a+b) + (c-d));
7 end
8 endfunction
9
10 endmodule