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Merge pull request #1143 from YosysHQ/clifford/fix1135
[yosys.git]
/
tests
/
asicworld
/
code_verilog_tutorial_simple_function.v
1
module simple_function();
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function myfunction;
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input a, b, c, d;
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begin
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myfunction = ((a+b) + (c-d));
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end
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endfunction
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endmodule