tests/asicworld/code_verilog_tutorial_task_global.v

   1 module task_global();
   2
   3 reg [7:0] temp_out;
   4 reg [7:0] temp_in;
   5
   6 task convert;
   7 begin
   8   temp_out = (9/5) *( temp_in + 32);
   9 end
  10 endtask
  11
  12 endmodule