tests/asicworld/code_verilog_tutorial_v2k_reg.v

   1 module v2k_reg();
   2
   3 // v2k allows to init variables
   4 reg a = 0;
   5 // Here only last variable is set to 0, i.e d = 0
   6 // Rest b, c are set to x
   7 reg b, c, d = 0;
   8 // reg data type can be signed in v2k
   9 // We can assign with signed constants
  10 reg signed [7:0] data = 8'shF0;
  11
  12 // Function can return signed values
  13 // Its ports can contain signed ports
  14 function signed [7:0] adder;
  15   input a_in;
  16   input b_in;
  17   input c_in;
  18   input signed [7:0] data_in;
  19   begin
  20     adder = a_in + b_in + c_in + data_in;
  21   end
  22 endfunction
  23
  24 endmodule