tests/asicworld/code_verilog_tutorial_which_clock.v

   1 module which_clock (x,y,q,d);
   2 input x,y,d;
   3 output q;
   4 reg q;
   5
   6 always @ (posedge x or posedge y)
   7    if (x)
   8      q <= 1'b0;
   9    else
  10      q <= d;
  11
  12 endmodule