tests/asicworld/xfirrtl

   1 # This file contains the names of verilog files to exclude from verilog to FIRRTL regression tests due to known failures.
   2 code_hdl_models_arbiter.v       error: reg rst; cannot be driven by primitives or continuous assignment.
   3 code_hdl_models_clk_div_45.v    yosys issue: 2nd PMUXTREE pass yields: ERROR: Negative edge clock on FF clk_div_45.$procdff$49.
   4 code_hdl_models_d_ff_gates.v    combinational loop
   5 code_hdl_models_d_latch_gates.v combinational loop
   6 code_hdl_models_dff_async_reset.v       $adff
   7 code_hdl_models_tff_async_reset.v       $adff
   8 code_hdl_models_uart.v  $adff
   9 code_tidbits_asyn_reset.v       $adff
  10 code_tidbits_reg_seq_example.v  $adff
  11 code_verilog_tutorial_always_example.v  empty module
  12 code_verilog_tutorial_escape_id.v       make_id issues (name begins with a digit)
  13 code_verilog_tutorial_explicit.v        firrtl backend bug (empty module)
  14 code_verilog_tutorial_first_counter.v   error: reg rst; cannot be driven by primitives or continuous assignment.
  15 code_verilog_tutorial_fsm_full.v        error: reg reset; cannot be driven by primitives or continuous assignment.
  16 code_verilog_tutorial_if_else.v empty module (everything is under 'always @ (posedge clk)')
  17 [code_verilog_tutorial_n_out_primitive.v        empty module
  18 code_verilog_tutorial_parallel_if.v     empty module (everything is under 'always @ (posedge clk)')
  19 code_verilog_tutorial_simple_function.v empty module (no hardware)
  20 code_verilog_tutorial_simple_if.v       empty module (everything is under 'always @ (posedge clk)')
  21 code_verilog_tutorial_task_global.v     empty module (everything is under 'always @ (posedge clk)')
  22 code_verilog_tutorial_v2k_reg.v         empty module
  23 code_verilog_tutorial_which_clock.v      $adff