tests/bram/generate.py

   1 #!/usr/bin/python
   2
   3 from __future__ import division
   4 from __future__ import print_function
   5
   6 import sys
   7 import random
   8
   9 def create_bram(dsc_f, sim_f, k1, k2):
  10     while True:
  11         init = random.randrange(2)
  12         abits  = random.randrange(1, 16)
  13         dbits  = random.randrange(1, 16)
  14         groups = random.randrange(5)
  15
  16         if random.randrange(2):
  17             abits = 2 ** random.randrange(1, 4)
  18         if random.randrange(2):
  19             dbits = 2 ** random.randrange(1, 4)
  20
  21         ports  = [ random.randrange(3) for i in range(groups) ]
  22         wrmode = [ random.randrange(2) for i in range(groups) ]
  23         enable = [ random.randrange(4) for i in range(groups) ]
  24         transp = [ random.randrange(4) for i in range(groups) ]
  25         clocks = [ random.randrange(4) for i in range(groups) ]
  26         clkpol = [ random.randrange(4) for i in range(groups) ]
  27
  28         for p1 in range(groups):
  29             if wrmode[p1] == 0:
  30                 enable[p1] = 0
  31             else:
  32                 enable[p1] = 2**enable[p1]
  33                 while dbits < enable[p1] or dbits % enable[p1] != 0:
  34                     enable[p1] //= 2
  35
  36         config_ok = True
  37         if wrmode.count(1) <= ports.count(0): config_ok = False
  38         if wrmode.count(0) <= ports.count(0): config_ok = False
  39         if config_ok: break
  40
  41     print('bram bram_%03d_%03d' % (k1, k2), file=dsc_f)
  42     print('  init %d' % init, file=dsc_f)
  43     print('  abits %d' % abits, file=dsc_f)
  44     print('  dbits %d' % dbits, file=dsc_f)
  45     print('  groups %d' % groups, file=dsc_f)
  46     print('  ports  %s' % " ".join(["%d" % i for i in ports]), file=dsc_f)
  47     print('  wrmode %s' % " ".join(["%d" % i for i in wrmode]), file=dsc_f)
  48     print('  enable %s' % " ".join(["%d" % i for i in enable]), file=dsc_f)
  49     print('  transp %s' % " ".join(["%d" % i for i in transp]), file=dsc_f)
  50     print('  clocks %s' % " ".join(["%d" % i for i in clocks]), file=dsc_f)
  51     print('  clkpol %s' % " ".join(["%d" % i for i in clkpol]), file=dsc_f)
  52     print('endbram', file=dsc_f)
  53     print('match bram_%03d_%03d' % (k1, k2), file=dsc_f)
  54     print('endmatch', file=dsc_f)
  55
  56     states = set()
  57     v_ports = set()
  58     v_stmts = list()
  59
  60     v_stmts.append("reg [%d:0] memory [0:%d];" % (dbits-1, 2**abits-1))
  61
  62     for p1 in range(groups):
  63         for p2 in range(ports[p1]):
  64             pf = "%c%d" % (chr(ord('A') + p1), p2 + 1)
  65
  66             if clocks[p1] and not ("CLK%d" % clocks[p1]) in v_ports:
  67                 v_ports.add("CLK%d" % clocks[p1])
  68                 v_stmts.append("input CLK%d;" % clocks[p1])
  69
  70             v_ports.add("%sADDR" % pf)
  71             v_stmts.append("input [%d:0] %sADDR;" % (abits-1, pf))
  72
  73             v_ports.add("%sDATA" % pf)
  74             v_stmts.append("%s [%d:0] %sDATA;" % ("input" if wrmode[p1] else "output reg", dbits-1, pf))
  75
  76             if wrmode[p1] and enable[p1]:
  77                 v_ports.add("%sEN" % pf)
  78                 v_stmts.append("input [%d:0] %sEN;" % (enable[p1]-1, pf))
  79
  80             assign_op = "<="
  81             if clocks[p1] == 0:
  82                 v_stmts.append("always @* begin")
  83                 assign_op = "="
  84             elif clkpol[p1] == 0:
  85                 v_stmts.append("always @(negedge CLK%d) begin" % clocks[p1])
  86             elif clkpol[p1] == 1:
  87                 v_stmts.append("always @(posedge CLK%d) begin" % clocks[p1])
  88             else:
  89                 if not ('CP', clkpol[p1]) in states:
  90                     v_stmts.append("parameter CLKPOL%d = 0;" % clkpol[p1])
  91                     states.add(('CP', clkpol[p1]))
  92                 if not ('CPW', clocks[p1], clkpol[p1]) in states:
  93                     v_stmts.append("wire CLK%d_CLKPOL%d = CLK%d == CLKPOL%d;" % (clocks[p1], clkpol[p1], clocks[p1], clkpol[p1]))
  94                     states.add(('CPW', clocks[p1], clkpol[p1]))
  95                 v_stmts.append("always @(posedge CLK%d_CLKPOL%d) begin" % (clocks[p1], clkpol[p1]))
  96
  97             if wrmode[p1]:
  98                 for i in range(enable[p1]):
  99                     enrange = "[%d:%d]" % ((i+1)*dbits/enable[p1]-1, i*dbits/enable[p1])
 100                     v_stmts.append("  if (%sEN[%d]) memory[%sADDR]%s %s %sDATA%s;" % (pf, i, pf, enrange, assign_op, pf, enrange))
 101             else:
 102                 v_stmts.append("  %sDATA %s memory[%sADDR];" % (pf, assign_op, pf))
 103             v_stmts.append("end")
 104
 105     print('module bram_%03d_%03d(%s);' % (k1, k2, ", ".join(v_ports)), file=sim_f)
 106     for stmt in v_stmts:
 107         print('  %s' % stmt, file=sim_f)
 108     print('endmodule', file=sim_f)
 109
 110 for k1 in range(10):
 111     dsc_f = file('temp/brams_%03d.txt' % k1, 'w');
 112     sim_f = file('temp/brams_%03d.v' % k1, 'w');
 113
 114     for k2 in range(10):
 115         create_bram(dsc_f, sim_f, k1, k2)
 116
 117     dsc_f.close()
 118     sim_f.close()
 119