2 from itertools
import count
4 from nmigen
.compat
import *
5 from nmigen
.compat
.genlib
.fsm
import FSM
7 from .support
import SimCase
10 class FSMCase(SimCase
, unittest
.TestCase
):
11 class TestBench(Module
):
15 self
.status
= Signal(8)
17 self
.submodules
.dut
= FSM()
25 NextState("SET-STATUS-LOW")
27 NextState("SET-STATUS")
30 self
.dut
.act("SET-STATUS",
31 NextValue(self
.status
, 0xaa),
34 self
.dut
.act("SET-STATUS-LOW",
35 NextValue(self
.status
[:4], 0xb),
39 def assertState(self
, fsm
, state
):
40 self
.assertEqual(fsm
.decoding
[(yield fsm
.state
)], state
)
42 def test_next_state(self
):
44 yield from self
.assertState(self
.tb
.dut
, "IDLE")
46 yield from self
.assertState(self
.tb
.dut
, "IDLE")
47 yield self
.tb
.ctrl
.eq(1)
49 yield from self
.assertState(self
.tb
.dut
, "IDLE")
50 yield self
.tb
.ctrl
.eq(0)
52 yield from self
.assertState(self
.tb
.dut
, "START")
54 yield from self
.assertState(self
.tb
.dut
, "SET-STATUS")
55 yield self
.tb
.ctrl
.eq(1)
57 yield from self
.assertState(self
.tb
.dut
, "IDLE")
58 yield self
.tb
.ctrl
.eq(0)
59 yield self
.tb
.data
.eq(1)
61 yield from self
.assertState(self
.tb
.dut
, "START")
62 yield self
.tb
.data
.eq(0)
64 yield from self
.assertState(self
.tb
.dut
, "SET-STATUS-LOW")
67 def test_next_value(self
):
69 self
.assertEqual((yield self
.tb
.status
), 0x00)
70 yield self
.tb
.ctrl
.eq(1)
72 yield self
.tb
.ctrl
.eq(0)
75 yield from self
.assertState(self
.tb
.dut
, "SET-STATUS")
76 yield self
.tb
.ctrl
.eq(1)
78 self
.assertEqual((yield self
.tb
.status
), 0xaa)
79 yield self
.tb
.ctrl
.eq(0)
80 yield self
.tb
.data
.eq(1)
82 yield self
.tb
.data
.eq(0)
84 yield from self
.assertState(self
.tb
.dut
, "SET-STATUS-LOW")
86 self
.assertEqual((yield self
.tb
.status
), 0xab)