mem: Allow read-only caches and check compliance
[gem5.git] / tests / configs / arm_generic.py
1 # Copyright (c) 2012 ARM Limited
2 # All rights reserved.
3 #
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
12 #
13 # Redistribution and use in source and binary forms, with or without
14 # modification, are permitted provided that the following conditions are
15 # met: redistributions of source code must retain the above copyright
16 # notice, this list of conditions and the following disclaimer;
17 # redistributions in binary form must reproduce the above copyright
18 # notice, this list of conditions and the following disclaimer in the
19 # documentation and/or other materials provided with the distribution;
20 # neither the name of the copyright holders nor the names of its
21 # contributors may be used to endorse or promote products derived from
22 # this software without specific prior written permission.
23 #
24 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #
36 # Authors: Andreas Sandberg
37
38 from abc import ABCMeta, abstractmethod
39 import m5
40 from m5.objects import *
41 from m5.proxy import *
42 m5.util.addToPath('../configs/common')
43 import FSConfig
44 from Caches import *
45 from base_config import *
46 from O3_ARM_v7a import *
47 from Benchmarks import SysConfig
48
49 class ArmSESystemUniprocessor(BaseSESystemUniprocessor):
50 """Syscall-emulation builder for ARM uniprocessor systems.
51
52 A small tweak of the syscall-emulation builder to use more
53 representative cache configurations.
54 """
55
56 def __init__(self, **kwargs):
57 BaseSESystem.__init__(self, **kwargs)
58
59 def create_caches_private(self, cpu):
60 # The atomic SE configurations do not use caches
61 if self.mem_mode == "timing":
62 # Use the more representative cache configuration
63 cpu.addTwoLevelCacheHierarchy(O3_ARM_v7a_ICache(),
64 O3_ARM_v7a_DCache(),
65 O3_ARM_v7aL2())
66
67 class LinuxArmSystemBuilder(object):
68 """Mix-in that implements create_system.
69
70 This mix-in is intended as a convenient way of adding an
71 ARM-specific create_system method to a class deriving from one of
72 the generic base systems.
73 """
74 def __init__(self, machine_type, **kwargs):
75 """
76 Arguments:
77 machine_type -- String describing the platform to simulate
78 num_cpus -- integer number of CPUs in the system
79 """
80 self.machine_type = machine_type
81 self.num_cpus = kwargs.get('num_cpus', 1)
82 self.mem_size = kwargs.get('mem_size', '256MB')
83
84 def create_system(self):
85 sc = SysConfig(None, self.mem_size, None)
86 system = FSConfig.makeArmSystem(self.mem_mode,
87 self.machine_type, self.num_cpus,
88 sc, False)
89
90 # We typically want the simulator to panic if the kernel
91 # panics or oopses. This prevents the simulator from running
92 # an obviously failed test case until the end of time.
93 system.panic_on_panic = True
94 system.panic_on_oops = True
95
96 self.init_system(system)
97 return system
98
99 class LinuxArmFSSystem(LinuxArmSystemBuilder,
100 BaseFSSystem):
101 """Basic ARM full system builder."""
102
103 def __init__(self, machine_type='VExpress_EMM', **kwargs):
104 """Initialize an ARM system that supports full system simulation.
105
106 Note: Keyword arguments that are not listed below will be
107 passed to the BaseFSSystem.
108
109 Keyword Arguments:
110 machine_type -- String describing the platform to simulate
111 """
112 BaseSystem.__init__(self, **kwargs)
113 LinuxArmSystemBuilder.__init__(self, machine_type, **kwargs)
114
115 def create_caches_private(self, cpu):
116 # Use the more representative cache configuration
117 cpu.addTwoLevelCacheHierarchy(O3_ARM_v7a_ICache(),
118 O3_ARM_v7a_DCache(),
119 O3_ARM_v7aL2())
120
121 class LinuxArmFSSystemUniprocessor(LinuxArmSystemBuilder,
122 BaseFSSystemUniprocessor):
123 """Basic ARM full system builder for uniprocessor systems.
124
125 Note: This class is a specialization of the ArmFSSystem and is
126 only really needed to provide backwards compatibility for existing
127 test cases.
128 """
129
130 def __init__(self, machine_type='VExpress_EMM', **kwargs):
131 BaseFSSystemUniprocessor.__init__(self, **kwargs)
132 LinuxArmSystemBuilder.__init__(self, machine_type, **kwargs)
133
134 class LinuxArmFSSwitcheroo(LinuxArmSystemBuilder, BaseFSSwitcheroo):
135 """Uniprocessor ARM system prepared for CPU switching"""
136
137 def __init__(self, machine_type='VExpress_EMM', **kwargs):
138 BaseFSSwitcheroo.__init__(self, **kwargs)
139 LinuxArmSystemBuilder.__init__(self, machine_type, **kwargs)