tests/configs/base_config.py

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  35
  36 from abc import ABCMeta, abstractmethod
  37 import optparse
  38 import m5
  39 from m5.objects import *
  40 from m5.proxy import *
  41 m5.util.addToPath('../configs/')
  42 from common import FSConfig
  43 from common import Options
  44 from common.Caches import *
  45 from ruby import Ruby
  46
  47 _have_kvm_support = 'BaseKvmCPU' in globals()
  48
  49 class BaseSystem(object):
  50     """Base system builder.
  51
  52     This class provides some basic functionality for creating an ARM
  53     system with the usual peripherals (caches, GIC, etc.). It allows
  54     customization by defining separate methods for different parts of
  55     the initialization process.
  56     """
  57
  58     __metaclass__ = ABCMeta
  59
  60     def __init__(self, mem_mode='timing', mem_class=SimpleMemory,
  61                  cpu_class=TimingSimpleCPU, num_cpus=1, num_threads=1,
  62                  checker=False, mem_size=None, use_ruby=False):
  63         """Initialize a simple base system.
  64
  65         Keyword Arguments:
  66           mem_mode -- String describing the memory mode (timing or atomic)
  67           mem_class -- Memory controller class to use
  68           cpu_class -- CPU class to use
  69           num_cpus -- Number of CPUs to instantiate
  70           checker -- Set to True to add checker CPUs
  71           mem_size -- Override the default memory size
  72           use_ruby -- Set to True to use ruby memory
  73         """
  74         self.mem_mode = mem_mode
  75         self.mem_class = mem_class
  76         self.cpu_class = cpu_class
  77         self.num_cpus = num_cpus
  78         self.num_threads = num_threads
  79         self.checker = checker
  80         self.use_ruby = use_ruby
  81
  82     def create_cpus(self, cpu_clk_domain):
  83         """Return a list of CPU objects to add to a system."""
  84         cpus = [ self.cpu_class(clk_domain=cpu_clk_domain,
  85                                 numThreads=self.num_threads,
  86                                 cpu_id=i)
  87                  for i in range(self.num_cpus) ]
  88         if self.checker:
  89             for c in cpus:
  90                 c.addCheckerCpu()
  91         return cpus
  92
  93     def create_caches_private(self, cpu):
  94         """Add private caches to a CPU.
  95
  96         Arguments:
  97           cpu -- CPU instance to work on.
  98         """
  99         cpu.addPrivateSplitL1Caches(L1_ICache(size='32kB', assoc=1),
 100                                     L1_DCache(size='32kB', assoc=4))
 101
 102     def create_caches_shared(self, system):
 103         """Add shared caches to a system.
 104
 105         Arguments:
 106           system -- System to work on.
 107
 108         Returns:
 109           A bus that CPUs should use to connect to the shared cache.
 110         """
 111         system.toL2Bus = L2XBar(clk_domain=system.cpu_clk_domain)
 112         system.l2c = L2Cache(clk_domain=system.cpu_clk_domain,
 113                              size='4MB', assoc=8)
 114         system.l2c.cpu_side = system.toL2Bus.master
 115         system.l2c.mem_side = system.membus.slave
 116         return system.toL2Bus
 117
 118     def init_cpu(self, system, cpu, sha_bus):
 119         """Initialize a CPU.
 120
 121         Arguments:
 122           system -- System to work on.
 123           cpu -- CPU to initialize.
 124         """
 125         if not cpu.switched_out:
 126             self.create_caches_private(cpu)
 127             cpu.createInterruptController()
 128             cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus,
 129                                 system.membus)
 130
 131     def init_kvm(self, system):
 132         """Do KVM-specific system initialization.
 133
 134         Arguments:
 135           system -- System to work on.
 136         """
 137         system.vm = KvmVM()
 138
 139     def init_system(self, system):
 140         """Initialize a system.
 141
 142         Arguments:
 143           system -- System to initialize.
 144         """
 145         self.create_clk_src(system)
 146         system.cpu = self.create_cpus(system.cpu_clk_domain)
 147
 148         if _have_kvm_support and \
 149                 any([isinstance(c, BaseKvmCPU) for c in system.cpu]):
 150             self.init_kvm(system)
 151
 152         if self.use_ruby:
 153             # Add the ruby specific and protocol specific options
 154             parser = optparse.OptionParser()
 155             Options.addCommonOptions(parser)
 156             Ruby.define_options(parser)
 157             (options, args) = parser.parse_args()
 158
 159             # Set the default cache size and associativity to be very
 160             # small to encourage races between requests and writebacks.
 161             options.l1d_size="32kB"
 162             options.l1i_size="32kB"
 163             options.l2_size="4MB"
 164             options.l1d_assoc=4
 165             options.l1i_assoc=2
 166             options.l2_assoc=8
 167             options.num_cpus = self.num_cpus
 168             options.num_dirs = 2
 169
 170             bootmem = getattr(system, '_bootmem', None)
 171             Ruby.create_system(options, True, system, system.iobus,
 172                                system._dma_ports, bootmem)
 173
 174             # Create a seperate clock domain for Ruby
 175             system.ruby.clk_domain = SrcClockDomain(
 176                 clock = options.ruby_clock,
 177                 voltage_domain = system.voltage_domain)
 178             for i, cpu in enumerate(system.cpu):
 179                 if not cpu.switched_out:
 180                     cpu.createInterruptController()
 181                     cpu.connectCachedPorts(system.ruby._cpu_ports[i])
 182         else:
 183             sha_bus = self.create_caches_shared(system)
 184             for cpu in system.cpu:
 185                 self.init_cpu(system, cpu, sha_bus)
 186
 187
 188     def create_clk_src(self,system):
 189         # Create system clock domain. This provides clock value to every
 190         # clocked object that lies beneath it unless explicitly overwritten
 191         # by a different clock domain.
 192         system.voltage_domain = VoltageDomain()
 193         system.clk_domain = SrcClockDomain(clock = '1GHz',
 194                                            voltage_domain =
 195                                            system.voltage_domain)
 196
 197         # Create a seperate clock domain for components that should
 198         # run at CPUs frequency
 199         system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
 200                                                voltage_domain =
 201                                                system.voltage_domain)
 202
 203     @abstractmethod
 204     def create_system(self):
 205         """Create an return an initialized system."""
 206         pass
 207
 208     @abstractmethod
 209     def create_root(self):
 210         """Create and return a simulation root using the system
 211         defined by this class."""
 212         pass
 213
 214 class BaseSESystem(BaseSystem):
 215     """Basic syscall-emulation builder."""
 216
 217     def __init__(self, **kwargs):
 218         super(BaseSESystem, self).__init__(**kwargs)
 219
 220     def init_system(self, system):
 221         super(BaseSESystem, self).init_system(system)
 222
 223     def create_system(self):
 224         system = System(physmem = self.mem_class(),
 225                         membus = SystemXBar(),
 226                         mem_mode = self.mem_mode,
 227                         multi_thread = (self.num_threads > 1))
 228         if not self.use_ruby:
 229             system.system_port = system.membus.slave
 230         system.physmem.port = system.membus.master
 231         self.init_system(system)
 232         return system
 233
 234     def create_root(self):
 235         system = self.create_system()
 236         m5.ticks.setGlobalFrequency('1THz')
 237         return Root(full_system=False, system=system)
 238
 239 class BaseSESystemUniprocessor(BaseSESystem):
 240     """Basic syscall-emulation builder for uniprocessor systems.
 241
 242     Note: This class is only really needed to provide backwards
 243     compatibility in existing test cases.
 244     """
 245
 246     def __init__(self, **kwargs):
 247         super(BaseSESystemUniprocessor, self).__init__(**kwargs)
 248
 249     def create_caches_private(self, cpu):
 250         # The atomic SE configurations do not use caches
 251         if self.mem_mode == "timing":
 252             # @todo We might want to revisit these rather enthusiastic L1 sizes
 253             cpu.addTwoLevelCacheHierarchy(L1_ICache(size='128kB'),
 254                                           L1_DCache(size='256kB'),
 255                                           L2Cache(size='2MB'))
 256
 257     def create_caches_shared(self, system):
 258         return None
 259
 260 class BaseFSSystem(BaseSystem):
 261     """Basic full system builder."""
 262
 263     def __init__(self, **kwargs):
 264         super(BaseFSSystem, self).__init__(**kwargs)
 265
 266     def init_system(self, system):
 267         super(BaseFSSystem, self).init_system(system)
 268
 269         if self.use_ruby:
 270             # Connect the ruby io port to the PIO bus,
 271             # assuming that there is just one such port.
 272             system.iobus.master = system.ruby._io_port.slave
 273         else:
 274             # create the memory controllers and connect them, stick with
 275             # the physmem name to avoid bumping all the reference stats
 276             system.physmem = [self.mem_class(range = r)
 277                               for r in system.mem_ranges]
 278             for i in range(len(system.physmem)):
 279                 system.physmem[i].port = system.membus.master
 280
 281             # create the iocache, which by default runs at the system clock
 282             system.iocache = IOCache(addr_ranges=system.mem_ranges)
 283             system.iocache.cpu_side = system.iobus.master
 284             system.iocache.mem_side = system.membus.slave
 285
 286     def create_root(self):
 287         system = self.create_system()
 288         m5.ticks.setGlobalFrequency('1THz')
 289         return Root(full_system=True, system=system)
 290
 291 class BaseFSSystemUniprocessor(BaseFSSystem):
 292     """Basic full system builder for uniprocessor systems.
 293
 294     Note: This class is only really needed to provide backwards
 295     compatibility in existing test cases.
 296     """
 297
 298     def __init__(self, **kwargs):
 299         super(BaseFSSystemUniprocessor, self).__init__(**kwargs)
 300
 301     def create_caches_private(self, cpu):
 302         cpu.addTwoLevelCacheHierarchy(L1_ICache(size='32kB', assoc=1),
 303                                       L1_DCache(size='32kB', assoc=4),
 304                                       L2Cache(size='4MB', assoc=8))
 305
 306     def create_caches_shared(self, system):
 307         return None
 308
 309 class BaseFSSwitcheroo(BaseFSSystem):
 310     """Uniprocessor system prepared for CPU switching"""
 311
 312     def __init__(self, cpu_classes, **kwargs):
 313         super(BaseFSSwitcheroo, self).__init__(**kwargs)
 314         self.cpu_classes = tuple(cpu_classes)
 315
 316     def create_cpus(self, cpu_clk_domain):
 317         cpus = [ cclass(clk_domain = cpu_clk_domain,
 318                         cpu_id=0,
 319                         switched_out=True)
 320                  for cclass in self.cpu_classes ]
 321         cpus[0].switched_out = False
 322         return cpus