1 # Copyright (c) 2012 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Redistribution and use in source and binary forms, with or without
14 # modification, are permitted provided that the following conditions are
15 # met: redistributions of source code must retain the above copyright
16 # notice, this list of conditions and the following disclaimer;
17 # redistributions in binary form must reproduce the above copyright
18 # notice, this list of conditions and the following disclaimer in the
19 # documentation and/or other materials provided with the distribution;
20 # neither the name of the copyright holders nor the names of its
21 # contributors may be used to endorse or promote products derived from
22 # this software without specific prior written permission.
24 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 # Authors: Andreas Sandberg
38 from abc
import ABCMeta
, abstractmethod
40 from m5
.objects
import *
41 from m5
.proxy
import *
42 m5
.util
.addToPath('../configs/common')
46 _have_kvm_support
= 'BaseKvmCPU' in globals()
48 class BaseSystem(object):
49 """Base system builder.
51 This class provides some basic functionality for creating an ARM
52 system with the usual peripherals (caches, GIC, etc.). It allows
53 customization by defining separate methods for different parts of
54 the initialization process.
57 __metaclass__
= ABCMeta
59 def __init__(self
, mem_mode
='timing', cpu_class
=TimingSimpleCPU
,
60 num_cpus
=1, checker
=False):
61 """Initialize a simple ARM system.
64 mem_mode -- String describing the memory mode (timing or atomic)
65 cpu_class -- CPU class to use
66 num_cpus -- Number of CPUs to instantiate
67 checker -- Set to True to add checker CPUs
69 self
.mem_mode
= mem_mode
70 self
.cpu_class
= cpu_class
71 self
.num_cpus
= num_cpus
72 self
.checker
= checker
74 def create_cpus(self
):
75 """Return a list of CPU objects to add to a system."""
76 cpus
= [ self
.cpu_class(cpu_id
=i
, clock
='2GHz')
77 for i
in range(self
.num_cpus
) ]
83 def create_caches_private(self
, cpu
):
84 """Add private caches to a CPU.
87 cpu -- CPU instance to work on.
89 cpu
.addPrivateSplitL1Caches(L1Cache(size
='32kB', assoc
=1),
90 L1Cache(size
='32kB', assoc
=4))
92 def create_caches_shared(self
, system
):
93 """Add shared caches to a system.
96 system -- System to work on.
99 A bus that CPUs should use to connect to the shared cache.
101 system
.toL2Bus
= CoherentBus(clock
='2GHz')
102 system
.l2c
= L2Cache(clock
='2GHz', size
='4MB', assoc
=8)
103 system
.l2c
.cpu_side
= system
.toL2Bus
.master
104 system
.l2c
.mem_side
= system
.membus
.slave
105 return system
.toL2Bus
107 def init_cpu(self
, system
, cpu
, sha_bus
):
111 system -- System to work on.
112 cpu -- CPU to initialize.
114 if not cpu
.switched_out
:
115 self
.create_caches_private(cpu
)
116 cpu
.createInterruptController()
117 cpu
.connectAllPorts(sha_bus
if sha_bus
!= None else system
.membus
,
120 def init_kvm(self
, system
):
121 """Do KVM-specific system initialization.
124 system -- System to work on.
128 def init_system(self
, system
):
129 """Initialize a system.
132 system -- System to initialize.
134 system
.cpu
= self
.create_cpus()
136 if _have_kvm_support
and \
137 any([isinstance(c
, BaseKvmCPU
) for c
in system
.cpu
]):
138 self
.init_kvm(system
)
140 sha_bus
= self
.create_caches_shared(system
)
141 for cpu
in system
.cpu
:
142 self
.init_cpu(system
, cpu
, sha_bus
)
145 def create_system(self
):
146 """Create an return an initialized system."""
150 def create_root(self
):
151 """Create and return a simulation root using the system
152 defined by this class."""
155 class BaseFSSystem(BaseSystem
):
156 """Basic full system builder."""
158 def __init__(self
, **kwargs
):
159 BaseSystem
.__init
__(self
, **kwargs
)
161 def init_system(self
, system
):
162 BaseSystem
.init_system(self
, system
)
165 system
.iocache
= IOCache(clock
='1GHz', addr_ranges
=system
.mem_ranges
)
166 system
.iocache
.cpu_side
= system
.iobus
.master
167 system
.iocache
.mem_side
= system
.membus
.slave
169 def create_root(self
):
170 system
= self
.create_system()
171 m5
.ticks
.setGlobalFrequency('1THz')
172 return Root(full_system
=True, system
=system
)
174 class BaseFSSystemUniprocessor(BaseFSSystem
):
175 """Basic full system builder for uniprocessor systems.
177 Note: This class is only really needed to provide backwards
178 compatibility in existing test cases.
181 def __init__(self
, **kwargs
):
182 BaseFSSystem
.__init
__(self
, **kwargs
)
184 def create_caches_private(self
, cpu
):
185 cpu
.addTwoLevelCacheHierarchy(L1Cache(size
='32kB', assoc
=1),
186 L1Cache(size
='32kB', assoc
=4),
187 L2Cache(size
='4MB', assoc
=8))
189 def create_caches_shared(self
, system
):
192 class BaseFSSwitcheroo(BaseFSSystem
):
193 """Uniprocessor system prepared for CPU switching"""
195 def __init__(self
, cpu_classes
, **kwargs
):
196 BaseFSSystem
.__init
__(self
, **kwargs
)
197 self
.cpu_classes
= tuple(cpu_classes
)
199 def create_cpus(self
):
200 cpus
= [ cclass(cpu_id
=0, clock
='2GHz', switched_out
=True)
201 for cclass
in self
.cpu_classes
]
202 cpus
[0].switched_out
= False