tests/configs/base_config.py

   1 # Copyright (c) 2012-2013 ARM Limited
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  35 #
  36 # Authors: Andreas Sandberg
  37 #          Andreas Hansson
  38
  39 from abc import ABCMeta, abstractmethod
  40 import m5
  41 from m5.objects import *
  42 from m5.proxy import *
  43 m5.util.addToPath('../configs/common')
  44 import FSConfig
  45 from Caches import *
  46
  47 _have_kvm_support = 'BaseKvmCPU' in globals()
  48
  49 class BaseSystem(object):
  50     """Base system builder.
  51
  52     This class provides some basic functionality for creating an ARM
  53     system with the usual peripherals (caches, GIC, etc.). It allows
  54     customization by defining separate methods for different parts of
  55     the initialization process.
  56     """
  57
  58     __metaclass__ = ABCMeta
  59
  60     def __init__(self, mem_mode='timing', mem_class=SimpleMemory,
  61                  cpu_class=TimingSimpleCPU, num_cpus=1, num_threads=1,
  62                  checker=False,
  63                  mem_size=None):
  64         """Initialize a simple base system.
  65
  66         Keyword Arguments:
  67           mem_mode -- String describing the memory mode (timing or atomic)
  68           mem_class -- Memory controller class to use
  69           cpu_class -- CPU class to use
  70           num_cpus -- Number of CPUs to instantiate
  71           checker -- Set to True to add checker CPUs
  72           mem_size -- Override the default memory size
  73         """
  74         self.mem_mode = mem_mode
  75         self.mem_class = mem_class
  76         self.cpu_class = cpu_class
  77         self.num_cpus = num_cpus
  78         self.num_threads = num_threads
  79         self.checker = checker
  80
  81     def create_cpus(self, cpu_clk_domain):
  82         """Return a list of CPU objects to add to a system."""
  83         cpus = [ self.cpu_class(clk_domain=cpu_clk_domain,
  84                                 numThreads=self.num_threads,
  85                                 cpu_id=i)
  86                  for i in range(self.num_cpus) ]
  87         if self.checker:
  88             for c in cpus:
  89                 c.addCheckerCpu()
  90         return cpus
  91
  92     def create_caches_private(self, cpu):
  93         """Add private caches to a CPU.
  94
  95         Arguments:
  96           cpu -- CPU instance to work on.
  97         """
  98         cpu.addPrivateSplitL1Caches(L1_ICache(size='32kB', assoc=1),
  99                                     L1_DCache(size='32kB', assoc=4))
 100
 101     def create_caches_shared(self, system):
 102         """Add shared caches to a system.
 103
 104         Arguments:
 105           system -- System to work on.
 106
 107         Returns:
 108           A bus that CPUs should use to connect to the shared cache.
 109         """
 110         system.toL2Bus = L2XBar(clk_domain=system.cpu_clk_domain)
 111         system.l2c = L2Cache(clk_domain=system.cpu_clk_domain,
 112                              size='4MB', assoc=8)
 113         system.l2c.cpu_side = system.toL2Bus.master
 114         system.l2c.mem_side = system.membus.slave
 115         return system.toL2Bus
 116
 117     def init_cpu(self, system, cpu, sha_bus):
 118         """Initialize a CPU.
 119
 120         Arguments:
 121           system -- System to work on.
 122           cpu -- CPU to initialize.
 123         """
 124         if not cpu.switched_out:
 125             self.create_caches_private(cpu)
 126             cpu.createInterruptController()
 127             cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus,
 128                                 system.membus)
 129
 130     def init_kvm(self, system):
 131         """Do KVM-specific system initialization.
 132
 133         Arguments:
 134           system -- System to work on.
 135         """
 136         system.vm = KvmVM()
 137
 138     def init_system(self, system):
 139         """Initialize a system.
 140
 141         Arguments:
 142           system -- System to initialize.
 143         """
 144         self.create_clk_src(system)
 145         system.cpu = self.create_cpus(system.cpu_clk_domain)
 146
 147         if _have_kvm_support and \
 148                 any([isinstance(c, BaseKvmCPU) for c in system.cpu]):
 149             self.init_kvm(system)
 150
 151         sha_bus = self.create_caches_shared(system)
 152         for cpu in system.cpu:
 153             self.init_cpu(system, cpu, sha_bus)
 154
 155     def create_clk_src(self,system):
 156         # Create system clock domain. This provides clock value to every
 157         # clocked object that lies beneath it unless explicitly overwritten
 158         # by a different clock domain.
 159         system.voltage_domain = VoltageDomain()
 160         system.clk_domain = SrcClockDomain(clock = '1GHz',
 161                                            voltage_domain =
 162                                            system.voltage_domain)
 163
 164         # Create a seperate clock domain for components that should
 165         # run at CPUs frequency
 166         system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
 167                                                voltage_domain =
 168                                                system.voltage_domain)
 169
 170     @abstractmethod
 171     def create_system(self):
 172         """Create an return an initialized system."""
 173         pass
 174
 175     @abstractmethod
 176     def create_root(self):
 177         """Create and return a simulation root using the system
 178         defined by this class."""
 179         pass
 180
 181 class BaseSESystem(BaseSystem):
 182     """Basic syscall-emulation builder."""
 183
 184     def __init__(self, **kwargs):
 185         BaseSystem.__init__(self, **kwargs)
 186
 187     def init_system(self, system):
 188         BaseSystem.init_system(self, system)
 189
 190     def create_system(self):
 191         system = System(physmem = self.mem_class(),
 192                         membus = SystemXBar(),
 193                         mem_mode = self.mem_mode,
 194                         multi_thread = (self.num_threads > 1))
 195         system.system_port = system.membus.slave
 196         system.physmem.port = system.membus.master
 197         self.init_system(system)
 198         return system
 199
 200     def create_root(self):
 201         system = self.create_system()
 202         m5.ticks.setGlobalFrequency('1THz')
 203         return Root(full_system=False, system=system)
 204
 205 class BaseSESystemUniprocessor(BaseSESystem):
 206     """Basic syscall-emulation builder for uniprocessor systems.
 207
 208     Note: This class is only really needed to provide backwards
 209     compatibility in existing test cases.
 210     """
 211
 212     def __init__(self, **kwargs):
 213         BaseSESystem.__init__(self, **kwargs)
 214
 215     def create_caches_private(self, cpu):
 216         # The atomic SE configurations do not use caches
 217         if self.mem_mode == "timing":
 218             # @todo We might want to revisit these rather enthusiastic L1 sizes
 219             cpu.addTwoLevelCacheHierarchy(L1_ICache(size='128kB'),
 220                                           L1_DCache(size='256kB'),
 221                                           L2Cache(size='2MB'))
 222
 223     def create_caches_shared(self, system):
 224         return None
 225
 226 class BaseFSSystem(BaseSystem):
 227     """Basic full system builder."""
 228
 229     def __init__(self, **kwargs):
 230         BaseSystem.__init__(self, **kwargs)
 231
 232     def init_system(self, system):
 233         BaseSystem.init_system(self, system)
 234
 235         # create the memory controllers and connect them, stick with
 236         # the physmem name to avoid bumping all the reference stats
 237         system.physmem = [self.mem_class(range = r)
 238                           for r in system.mem_ranges]
 239         for i in xrange(len(system.physmem)):
 240             system.physmem[i].port = system.membus.master
 241
 242         # create the iocache, which by default runs at the system clock
 243         system.iocache = IOCache(addr_ranges=system.mem_ranges)
 244         system.iocache.cpu_side = system.iobus.master
 245         system.iocache.mem_side = system.membus.slave
 246
 247     def create_root(self):
 248         system = self.create_system()
 249         m5.ticks.setGlobalFrequency('1THz')
 250         return Root(full_system=True, system=system)
 251
 252 class BaseFSSystemUniprocessor(BaseFSSystem):
 253     """Basic full system builder for uniprocessor systems.
 254
 255     Note: This class is only really needed to provide backwards
 256     compatibility in existing test cases.
 257     """
 258
 259     def __init__(self, **kwargs):
 260         BaseFSSystem.__init__(self, **kwargs)
 261
 262     def create_caches_private(self, cpu):
 263         cpu.addTwoLevelCacheHierarchy(L1_ICache(size='32kB', assoc=1),
 264                                       L1_DCache(size='32kB', assoc=4),
 265                                       L2Cache(size='4MB', assoc=8))
 266
 267     def create_caches_shared(self, system):
 268         return None
 269
 270 class BaseFSSwitcheroo(BaseFSSystem):
 271     """Uniprocessor system prepared for CPU switching"""
 272
 273     def __init__(self, cpu_classes, **kwargs):
 274         BaseFSSystem.__init__(self, **kwargs)
 275         self.cpu_classes = tuple(cpu_classes)
 276
 277     def create_cpus(self, cpu_clk_domain):
 278         cpus = [ cclass(clk_domain = cpu_clk_domain,
 279                         cpu_id=0,
 280                         switched_out=True)
 281                  for cclass in self.cpu_classes ]
 282         cpus[0].switched_out = False
 283         return cpus