tests/configs/base_config.py

   1 # Copyright (c) 2012-2013 ARM Limited
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  35 #
  36 # Authors: Andreas Sandberg
  37 #          Andreas Hansson
  38
  39 from abc import ABCMeta, abstractmethod
  40 import m5
  41 from m5.objects import *
  42 from m5.proxy import *
  43 m5.util.addToPath('../configs/common')
  44 import FSConfig
  45 from Caches import *
  46
  47 _have_kvm_support = 'BaseKvmCPU' in globals()
  48
  49 class BaseSystem(object):
  50     """Base system builder.
  51
  52     This class provides some basic functionality for creating an ARM
  53     system with the usual peripherals (caches, GIC, etc.). It allows
  54     customization by defining separate methods for different parts of
  55     the initialization process.
  56     """
  57
  58     __metaclass__ = ABCMeta
  59
  60     def __init__(self, mem_mode='timing', mem_class=SimpleMemory,
  61                  cpu_class=TimingSimpleCPU, num_cpus=1, num_threads=1,
  62                  checker=False,
  63                  mem_size=None):
  64         """Initialize a simple base system.
  65
  66         Keyword Arguments:
  67           mem_mode -- String describing the memory mode (timing or atomic)
  68           mem_class -- Memory controller class to use
  69           cpu_class -- CPU class to use
  70           num_cpus -- Number of CPUs to instantiate
  71           checker -- Set to True to add checker CPUs
  72           mem_size -- Override the default memory size
  73         """
  74         self.mem_mode = mem_mode
  75         self.mem_class = mem_class
  76         self.cpu_class = cpu_class
  77         self.num_cpus = num_cpus
  78         self.num_threads = num_threads
  79         self.checker = checker
  80
  81     def create_cpus(self, cpu_clk_domain):
  82         """Return a list of CPU objects to add to a system."""
  83         cpus = [ self.cpu_class(clk_domain=cpu_clk_domain,
  84                                 numThreads=self.num_threads,
  85                                 cpu_id=i)
  86                  for i in range(self.num_cpus) ]
  87         if self.checker:
  88             for c in cpus:
  89                 c.addCheckerCpu()
  90         return cpus
  91
  92     def create_caches_private(self, cpu):
  93         """Add private caches to a CPU.
  94
  95         Arguments:
  96           cpu -- CPU instance to work on.
  97         """
  98         cpu.addPrivateSplitL1Caches(L1_ICache(size='32kB', assoc=1),
  99                                     L1_DCache(size='32kB', assoc=4))
 100
 101     def create_caches_shared(self, system):
 102         """Add shared caches to a system.
 103
 104         Arguments:
 105           system -- System to work on.
 106
 107         Returns:
 108           A bus that CPUs should use to connect to the shared cache.
 109         """
 110         system.toL2Bus = L2XBar(clk_domain=system.cpu_clk_domain)
 111         system.l2c = L2Cache(clk_domain=system.cpu_clk_domain,
 112                              size='4MB', assoc=8)
 113         system.l2c.cpu_side = system.toL2Bus.master
 114         system.l2c.mem_side = system.membus.slave
 115         return system.toL2Bus
 116
 117     def init_cpu(self, system, cpu, sha_bus):
 118         """Initialize a CPU.
 119
 120         Arguments:
 121           system -- System to work on.
 122           cpu -- CPU to initialize.
 123         """
 124         if not cpu.switched_out:
 125             self.create_caches_private(cpu)
 126             cpu.createInterruptController()
 127             cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus,
 128                                 system.membus)
 129             # System has caches before the membus -> add snoop filter
 130             if sha_bus and system.membus.snoop_filter == NULL:
 131                 system.membus.snoop_filter = SnoopFilter()
 132
 133     def init_kvm(self, system):
 134         """Do KVM-specific system initialization.
 135
 136         Arguments:
 137           system -- System to work on.
 138         """
 139         system.vm = KvmVM()
 140
 141     def init_system(self, system):
 142         """Initialize a system.
 143
 144         Arguments:
 145           system -- System to initialize.
 146         """
 147         self.create_clk_src(system)
 148         system.cpu = self.create_cpus(system.cpu_clk_domain)
 149
 150         if _have_kvm_support and \
 151                 any([isinstance(c, BaseKvmCPU) for c in system.cpu]):
 152             self.init_kvm(system)
 153
 154         sha_bus = self.create_caches_shared(system)
 155         # System has caches before the membus -> add snoop filter
 156         if sha_bus and system.membus.snoop_filter == NULL:
 157             system.membus.snoop_filter = SnoopFilter()
 158         for cpu in system.cpu:
 159             self.init_cpu(system, cpu, sha_bus)
 160
 161     def create_clk_src(self,system):
 162         # Create system clock domain. This provides clock value to every
 163         # clocked object that lies beneath it unless explicitly overwritten
 164         # by a different clock domain.
 165         system.voltage_domain = VoltageDomain()
 166         system.clk_domain = SrcClockDomain(clock = '1GHz',
 167                                            voltage_domain =
 168                                            system.voltage_domain)
 169
 170         # Create a seperate clock domain for components that should
 171         # run at CPUs frequency
 172         system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
 173                                                voltage_domain =
 174                                                system.voltage_domain)
 175
 176     @abstractmethod
 177     def create_system(self):
 178         """Create an return an initialized system."""
 179         pass
 180
 181     @abstractmethod
 182     def create_root(self):
 183         """Create and return a simulation root using the system
 184         defined by this class."""
 185         pass
 186
 187 class BaseSESystem(BaseSystem):
 188     """Basic syscall-emulation builder."""
 189
 190     def __init__(self, **kwargs):
 191         BaseSystem.__init__(self, **kwargs)
 192
 193     def init_system(self, system):
 194         BaseSystem.init_system(self, system)
 195
 196     def create_system(self):
 197         system = System(physmem = self.mem_class(),
 198                         membus = SystemXBar(),
 199                         mem_mode = self.mem_mode,
 200                         multi_thread = (self.num_threads > 1))
 201         system.system_port = system.membus.slave
 202         system.physmem.port = system.membus.master
 203         self.init_system(system)
 204         return system
 205
 206     def create_root(self):
 207         system = self.create_system()
 208         m5.ticks.setGlobalFrequency('1THz')
 209         return Root(full_system=False, system=system)
 210
 211 class BaseSESystemUniprocessor(BaseSESystem):
 212     """Basic syscall-emulation builder for uniprocessor systems.
 213
 214     Note: This class is only really needed to provide backwards
 215     compatibility in existing test cases.
 216     """
 217
 218     def __init__(self, **kwargs):
 219         BaseSESystem.__init__(self, **kwargs)
 220
 221     def create_caches_private(self, cpu):
 222         # The atomic SE configurations do not use caches
 223         if self.mem_mode == "timing":
 224             # @todo We might want to revisit these rather enthusiastic L1 sizes
 225             cpu.addTwoLevelCacheHierarchy(L1_ICache(size='128kB'),
 226                                           L1_DCache(size='256kB'),
 227                                           L2Cache(size='2MB'))
 228
 229     def create_caches_shared(self, system):
 230         return None
 231
 232 class BaseFSSystem(BaseSystem):
 233     """Basic full system builder."""
 234
 235     def __init__(self, **kwargs):
 236         BaseSystem.__init__(self, **kwargs)
 237
 238     def init_system(self, system):
 239         BaseSystem.init_system(self, system)
 240
 241         # create the memory controllers and connect them, stick with
 242         # the physmem name to avoid bumping all the reference stats
 243         system.physmem = [self.mem_class(range = r)
 244                           for r in system.mem_ranges]
 245         for i in xrange(len(system.physmem)):
 246             system.physmem[i].port = system.membus.master
 247
 248         # create the iocache, which by default runs at the system clock
 249         system.iocache = IOCache(addr_ranges=system.mem_ranges)
 250         system.iocache.cpu_side = system.iobus.master
 251         system.iocache.mem_side = system.membus.slave
 252
 253     def create_root(self):
 254         system = self.create_system()
 255         m5.ticks.setGlobalFrequency('1THz')
 256         return Root(full_system=True, system=system)
 257
 258 class BaseFSSystemUniprocessor(BaseFSSystem):
 259     """Basic full system builder for uniprocessor systems.
 260
 261     Note: This class is only really needed to provide backwards
 262     compatibility in existing test cases.
 263     """
 264
 265     def __init__(self, **kwargs):
 266         BaseFSSystem.__init__(self, **kwargs)
 267
 268     def create_caches_private(self, cpu):
 269         cpu.addTwoLevelCacheHierarchy(L1_ICache(size='32kB', assoc=1),
 270                                       L1_DCache(size='32kB', assoc=4),
 271                                       L2Cache(size='4MB', assoc=8))
 272
 273     def create_caches_shared(self, system):
 274         return None
 275
 276 class BaseFSSwitcheroo(BaseFSSystem):
 277     """Uniprocessor system prepared for CPU switching"""
 278
 279     def __init__(self, cpu_classes, **kwargs):
 280         BaseFSSystem.__init__(self, **kwargs)
 281         self.cpu_classes = tuple(cpu_classes)
 282
 283     def create_cpus(self, cpu_clk_domain):
 284         cpus = [ cclass(clk_domain = cpu_clk_domain,
 285                         cpu_id=0,
 286                         switched_out=True)
 287                  for cclass in self.cpu_classes ]
 288         cpus[0].switched_out = False
 289         return cpus