1 # Copyright (c) 2012-2013 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Redistribution and use in source and binary forms, with or without
14 # modification, are permitted provided that the following conditions are
15 # met: redistributions of source code must retain the above copyright
16 # notice, this list of conditions and the following disclaimer;
17 # redistributions in binary form must reproduce the above copyright
18 # notice, this list of conditions and the following disclaimer in the
19 # documentation and/or other materials provided with the distribution;
20 # neither the name of the copyright holders nor the names of its
21 # contributors may be used to endorse or promote products derived from
22 # this software without specific prior written permission.
24 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 # Authors: Andreas Sandberg
39 from abc
import ABCMeta
, abstractmethod
41 from m5
.objects
import *
42 from m5
.proxy
import *
43 m5
.util
.addToPath('../configs/common')
47 _have_kvm_support
= 'BaseKvmCPU' in globals()
49 class BaseSystem(object):
50 """Base system builder.
52 This class provides some basic functionality for creating an ARM
53 system with the usual peripherals (caches, GIC, etc.). It allows
54 customization by defining separate methods for different parts of
55 the initialization process.
58 __metaclass__
= ABCMeta
60 def __init__(self
, mem_mode
='timing', mem_class
=SimpleMemory
,
61 cpu_class
=TimingSimpleCPU
, num_cpus
=1, checker
=False,
63 """Initialize a simple base system.
66 mem_mode -- String describing the memory mode (timing or atomic)
67 mem_class -- Memory controller class to use
68 cpu_class -- CPU class to use
69 num_cpus -- Number of CPUs to instantiate
70 checker -- Set to True to add checker CPUs
71 mem_size -- Override the default memory size
73 self
.mem_mode
= mem_mode
74 self
.mem_class
= mem_class
75 self
.cpu_class
= cpu_class
76 self
.num_cpus
= num_cpus
77 self
.checker
= checker
79 def create_cpus(self
, cpu_clk_domain
):
80 """Return a list of CPU objects to add to a system."""
81 cpus
= [ self
.cpu_class(clk_domain
= cpu_clk_domain
,
83 for i
in range(self
.num_cpus
) ]
89 def create_caches_private(self
, cpu
):
90 """Add private caches to a CPU.
93 cpu -- CPU instance to work on.
95 cpu
.addPrivateSplitL1Caches(L1Cache(size
='32kB', assoc
=1),
96 L1Cache(size
='32kB', assoc
=4))
98 def create_caches_shared(self
, system
):
99 """Add shared caches to a system.
102 system -- System to work on.
105 A bus that CPUs should use to connect to the shared cache.
107 system
.toL2Bus
= CoherentXBar(clk_domain
=system
.cpu_clk_domain
)
108 system
.l2c
= L2Cache(clk_domain
=system
.cpu_clk_domain
,
110 system
.l2c
.cpu_side
= system
.toL2Bus
.master
111 system
.l2c
.mem_side
= system
.membus
.slave
112 return system
.toL2Bus
114 def init_cpu(self
, system
, cpu
, sha_bus
):
118 system -- System to work on.
119 cpu -- CPU to initialize.
121 if not cpu
.switched_out
:
122 self
.create_caches_private(cpu
)
123 cpu
.createInterruptController()
124 cpu
.connectAllPorts(sha_bus
if sha_bus
!= None else system
.membus
,
127 def init_kvm(self
, system
):
128 """Do KVM-specific system initialization.
131 system -- System to work on.
135 def init_system(self
, system
):
136 """Initialize a system.
139 system -- System to initialize.
141 self
.create_clk_src(system
)
142 system
.cpu
= self
.create_cpus(system
.cpu_clk_domain
)
144 if _have_kvm_support
and \
145 any([isinstance(c
, BaseKvmCPU
) for c
in system
.cpu
]):
146 self
.init_kvm(system
)
148 sha_bus
= self
.create_caches_shared(system
)
149 for cpu
in system
.cpu
:
150 self
.init_cpu(system
, cpu
, sha_bus
)
152 def create_clk_src(self
,system
):
153 # Create system clock domain. This provides clock value to every
154 # clocked object that lies beneath it unless explicitly overwritten
155 # by a different clock domain.
156 system
.voltage_domain
= VoltageDomain()
157 system
.clk_domain
= SrcClockDomain(clock
= '1GHz',
159 system
.voltage_domain
)
161 # Create a seperate clock domain for components that should
162 # run at CPUs frequency
163 system
.cpu_clk_domain
= SrcClockDomain(clock
= '2GHz',
165 system
.voltage_domain
)
168 def create_system(self
):
169 """Create an return an initialized system."""
173 def create_root(self
):
174 """Create and return a simulation root using the system
175 defined by this class."""
178 class BaseSESystem(BaseSystem
):
179 """Basic syscall-emulation builder."""
181 def __init__(self
, **kwargs
):
182 BaseSystem
.__init
__(self
, **kwargs
)
184 def init_system(self
, system
):
185 BaseSystem
.init_system(self
, system
)
187 def create_system(self
):
188 system
= System(physmem
= self
.mem_class(),
189 membus
= CoherentXBar(),
190 mem_mode
= self
.mem_mode
)
191 system
.system_port
= system
.membus
.slave
192 system
.physmem
.port
= system
.membus
.master
193 self
.init_system(system
)
196 def create_root(self
):
197 system
= self
.create_system()
198 m5
.ticks
.setGlobalFrequency('1THz')
199 return Root(full_system
=False, system
=system
)
201 class BaseSESystemUniprocessor(BaseSESystem
):
202 """Basic syscall-emulation builder for uniprocessor systems.
204 Note: This class is only really needed to provide backwards
205 compatibility in existing test cases.
208 def __init__(self
, **kwargs
):
209 BaseSESystem
.__init
__(self
, **kwargs
)
211 def create_caches_private(self
, cpu
):
212 # The atomic SE configurations do not use caches
213 if self
.mem_mode
== "timing":
214 # @todo We might want to revisit these rather enthusiastic L1 sizes
215 cpu
.addTwoLevelCacheHierarchy(L1Cache(size
='128kB'),
216 L1Cache(size
='256kB'),
219 def create_caches_shared(self
, system
):
222 class BaseFSSystem(BaseSystem
):
223 """Basic full system builder."""
225 def __init__(self
, **kwargs
):
226 BaseSystem
.__init
__(self
, **kwargs
)
228 def init_system(self
, system
):
229 BaseSystem
.init_system(self
, system
)
231 # create the memory controllers and connect them, stick with
232 # the physmem name to avoid bumping all the reference stats
233 system
.physmem
= [self
.mem_class(range = r
)
234 for r
in system
.mem_ranges
]
235 for i
in xrange(len(system
.physmem
)):
236 system
.physmem
[i
].port
= system
.membus
.master
238 # create the iocache, which by default runs at the system clock
239 system
.iocache
= IOCache(addr_ranges
=system
.mem_ranges
)
240 system
.iocache
.cpu_side
= system
.iobus
.master
241 system
.iocache
.mem_side
= system
.membus
.slave
243 def create_root(self
):
244 system
= self
.create_system()
245 m5
.ticks
.setGlobalFrequency('1THz')
246 return Root(full_system
=True, system
=system
)
248 class BaseFSSystemUniprocessor(BaseFSSystem
):
249 """Basic full system builder for uniprocessor systems.
251 Note: This class is only really needed to provide backwards
252 compatibility in existing test cases.
255 def __init__(self
, **kwargs
):
256 BaseFSSystem
.__init
__(self
, **kwargs
)
258 def create_caches_private(self
, cpu
):
259 cpu
.addTwoLevelCacheHierarchy(L1Cache(size
='32kB', assoc
=1),
260 L1Cache(size
='32kB', assoc
=4),
261 L2Cache(size
='4MB', assoc
=8))
263 def create_caches_shared(self
, system
):
266 class BaseFSSwitcheroo(BaseFSSystem
):
267 """Uniprocessor system prepared for CPU switching"""
269 def __init__(self
, cpu_classes
, **kwargs
):
270 BaseFSSystem
.__init
__(self
, **kwargs
)
271 self
.cpu_classes
= tuple(cpu_classes
)
273 def create_cpus(self
, cpu_clk_domain
):
274 cpus
= [ cclass(clk_domain
= cpu_clk_domain
,
277 for cclass
in self
.cpu_classes
]
278 cpus
[0].switched_out
= False