tests/configs/memtest-filter.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # All rights reserved.
   3 #
   4 # Redistribution and use in source and binary forms, with or without
   5 # modification, are permitted provided that the following conditions are
   6 # met: redistributions of source code must retain the above copyright
   7 # notice, this list of conditions and the following disclaimer;
   8 # redistributions in binary form must reproduce the above copyright
   9 # notice, this list of conditions and the following disclaimer in the
  10 # documentation and/or other materials provided with the distribution;
  11 # neither the name of the copyright holders nor the names of its
  12 # contributors may be used to endorse or promote products derived from
  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26
  27 import m5
  28 from m5.objects import *
  29 m5.util.addToPath('../configs/')
  30 from common.Caches import *
  31
  32 #MAX CORES IS 8 with the fals sharing method
  33 nb_cores = 8
  34 cpus = [ MemTest() for i in range(nb_cores) ]
  35
  36 # system simulated
  37 system = System(cpu = cpus,
  38                 physmem = SimpleMemory(),
  39                 membus = SystemXBar(width=16, snoop_filter = SnoopFilter()))
  40 # Dummy voltage domain for all our clock domains
  41 system.voltage_domain = VoltageDomain()
  42 system.clk_domain = SrcClockDomain(clock = '1GHz',
  43                                    voltage_domain = system.voltage_domain)
  44
  45 # Create a seperate clock domain for components that should run at
  46 # CPUs frequency
  47 system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
  48                                        voltage_domain = system.voltage_domain)
  49
  50 system.toL2Bus = L2XBar(clk_domain = system.cpu_clk_domain,
  51                         snoop_filter = SnoopFilter())
  52 system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8)
  53 system.l2c.cpu_side = system.toL2Bus.master
  54
  55 # connect l2c to membus
  56 system.l2c.mem_side = system.membus.slave
  57
  58 # add L1 caches
  59 for cpu in cpus:
  60     # All cpus are associated with cpu_clk_domain
  61     cpu.clk_domain = system.cpu_clk_domain
  62     cpu.l1c = L1Cache(size = '32kB', assoc = 4)
  63     cpu.l1c.cpu_side = cpu.port
  64     cpu.l1c.mem_side = system.toL2Bus.slave
  65
  66 system.system_port = system.membus.slave
  67
  68 # connect memory to membus
  69 system.physmem.port = system.membus.master
  70
  71
  72 # -----------------------
  73 # run simulation
  74 # -----------------------
  75
  76 root = Root( full_system = False, system = system )
  77 root.system.mem_mode = 'timing'