1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
4 # Redistribution and use in source and binary forms, with or without
5 # modification, are permitted provided that the following conditions are
6 # met: redistributions of source code must retain the above copyright
7 # notice, this list of conditions and the following disclaimer;
8 # redistributions in binary form must reproduce the above copyright
9 # notice, this list of conditions and the following disclaimer in the
10 # documentation and/or other materials provided with the distribution;
11 # neither the name of the copyright holders nor the names of its
12 # contributors may be used to endorse or promote products derived from
13 # this software without specific prior written permission.
15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 # Authors: Ron Dreslinski
30 from m5
.objects
import *
31 m5
.util
.addToPath('../configs/common')
34 #MAX CORES IS 8 with the fals sharing method
36 cpus
= [ MemTest() for i
in xrange(nb_cores
) ]
39 system
= System(cpu
= cpus
, funcmem
= SimpleMemory(in_addr_map
= False),
40 funcbus
= NoncoherentBus(),
41 physmem
= SimpleMemory(),
42 membus
= CoherentBus(width
=16, snoop_filter
= SnoopFilter()))
43 # Dummy voltage domain for all our clock domains
44 system
.voltage_domain
= VoltageDomain()
45 system
.clk_domain
= SrcClockDomain(clock
= '1GHz',
46 voltage_domain
= system
.voltage_domain
)
48 # Create a seperate clock domain for components that should run at
50 system
.cpu_clk_domain
= SrcClockDomain(clock
= '2GHz',
51 voltage_domain
= system
.voltage_domain
)
53 system
.toL2Bus
= CoherentBus(clk_domain
= system
.cpu_clk_domain
, width
=16,
54 snoop_filter
= SnoopFilter())
55 system
.l2c
= L2Cache(clk_domain
= system
.cpu_clk_domain
, size
='64kB', assoc
=8)
56 system
.l2c
.cpu_side
= system
.toL2Bus
.master
58 # connect l2c to membus
59 system
.l2c
.mem_side
= system
.membus
.slave
63 # All cpus are associated with cpu_clk_domain
64 cpu
.clk_domain
= system
.cpu_clk_domain
65 cpu
.l1c
= L1Cache(size
= '32kB', assoc
= 4)
66 cpu
.l1c
.cpu_side
= cpu
.test
67 cpu
.l1c
.mem_side
= system
.toL2Bus
.slave
68 system
.funcbus
.slave
= cpu
.functional
70 system
.system_port
= system
.membus
.slave
72 # connect reference memory to funcbus
73 system
.funcmem
.port
= system
.funcbus
.master
75 # connect memory to membus
76 system
.physmem
.port
= system
.membus
.master
79 # -----------------------
81 # -----------------------
83 root
= Root( full_system
= False, system
= system
)
84 root
.system
.mem_mode
= 'timing'
85 #root.trace.flags="Cache CachePort MemoryAccess"