tests/configs/memtest-ruby.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # Copyright (c) 2010 Advanced Micro Devices, Inc.
   3 # All rights reserved.
   4 #
   5 # Redistribution and use in source and binary forms, with or without
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   8 # notice, this list of conditions and the following disclaimer;
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  10 # notice, this list of conditions and the following disclaimer in the
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  12 # neither the name of the copyright holders nor the names of its
  13 # contributors may be used to endorse or promote products derived from
  14 # this software without specific prior written permission.
  15 #
  16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  20 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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  25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27 #
  28 # Authors: Ron Dreslinski
  29
  30 import m5
  31 from m5.objects import *
  32 from m5.defines import buildEnv
  33 from m5.util import addToPath
  34 import os, optparse, sys
  35
  36 m5.util.addToPath('../configs/')
  37
  38 from ruby import Ruby
  39 from common import Options
  40
  41 parser = optparse.OptionParser()
  42 Options.addCommonOptions(parser)
  43
  44 # Add the ruby specific and protocol specific options
  45 Ruby.define_options(parser)
  46
  47 (options, args) = parser.parse_args()
  48
  49 #
  50 # Set the default cache size and associativity to be very small to encourage
  51 # races between requests and writebacks.
  52 #
  53 options.l1d_size="256B"
  54 options.l1i_size="256B"
  55 options.l2_size="512B"
  56 options.l3_size="1kB"
  57 options.l1d_assoc=2
  58 options.l1i_assoc=2
  59 options.l2_assoc=2
  60 options.l3_assoc=2
  61 options.ports=32
  62
  63 #MAX CORES IS 8 with the fals sharing method
  64 nb_cores = 8
  65
  66 # ruby does not support atomic, functional, or uncacheable accesses
  67 cpus = [ MemTest(percent_functional=50,
  68                  percent_uncacheable=0, suppress_func_warnings=True) \
  69          for i in range(nb_cores) ]
  70
  71 # overwrite options.num_cpus with the nb_cores value
  72 options.num_cpus = nb_cores
  73
  74 # system simulated
  75 system = System(cpu = cpus)
  76 # Dummy voltage domain for all our clock domains
  77 system.voltage_domain = VoltageDomain()
  78 system.clk_domain = SrcClockDomain(clock = '1GHz',
  79                                    voltage_domain = system.voltage_domain)
  80
  81 # Create a seperate clock domain for components that should run at
  82 # CPUs frequency
  83 system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
  84                                        voltage_domain = system.voltage_domain)
  85
  86 # All cpus are associated with cpu_clk_domain
  87 for cpu in cpus:
  88     cpu.clk_domain = system.cpu_clk_domain
  89
  90 system.mem_ranges = AddrRange('256MB')
  91
  92 Ruby.create_system(options, False, system)
  93
  94 # Create a separate clock domain for Ruby
  95 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
  96                                         voltage_domain = system.voltage_domain)
  97
  98 assert(len(cpus) == len(system.ruby._cpu_ports))
  99
 100 for (i, ruby_port) in enumerate(system.ruby._cpu_ports):
 101      #
 102      # Tie the cpu port to the ruby cpu ports and
 103      # physmem, respectively
 104      #
 105      cpus[i].port = ruby_port.slave
 106
 107      #
 108      # Since the memtester is incredibly bursty, increase the deadlock
 109      # threshold to 1 million cycles
 110      #
 111      ruby_port.deadlock_threshold = 1000000
 112
 113 # -----------------------
 114 # run simulation
 115 # -----------------------
 116
 117 root = Root(full_system = False, system = system)
 118 root.system.mem_mode = 'timing'