tests/configs/memtest-ruby.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # Copyright (c) 2010 Advanced Micro Devices, Inc.
   3 # All rights reserved.
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  13 # contributors may be used to endorse or promote products derived from
  14 # this software without specific prior written permission.
  15 #
  16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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  27 #
  28 # Authors: Ron Dreslinski
  29
  30 import m5
  31 from m5.objects import *
  32 from m5.defines import buildEnv
  33 from m5.util import addToPath
  34 import os, optparse, sys
  35
  36 # Get paths we might need
  37 config_path = os.path.dirname(os.path.abspath(__file__))
  38 config_root = os.path.dirname(config_path)
  39 m5_root = os.path.dirname(config_root)
  40 addToPath(config_root+'/configs/common')
  41 addToPath(config_root+'/configs/ruby')
  42 addToPath(config_root+'/configs/topologies')
  43
  44 import Ruby
  45 import Options
  46
  47 parser = optparse.OptionParser()
  48 Options.addCommonOptions(parser)
  49
  50 # Add the ruby specific and protocol specific options
  51 Ruby.define_options(parser)
  52
  53 (options, args) = parser.parse_args()
  54
  55 #
  56 # Set the default cache size and associativity to be very small to encourage
  57 # races between requests and writebacks.
  58 #
  59 options.l1d_size="256B"
  60 options.l1i_size="256B"
  61 options.l2_size="512B"
  62 options.l3_size="1kB"
  63 options.l1d_assoc=2
  64 options.l1i_assoc=2
  65 options.l2_assoc=2
  66 options.l3_assoc=2
  67 options.ports=32
  68
  69 #MAX CORES IS 8 with the fals sharing method
  70 nb_cores = 8
  71
  72 # ruby does not support atomic, functional, or uncacheable accesses
  73 cpus = [ MemTest(percent_functional=50,
  74                  percent_uncacheable=0, suppress_func_warnings=True) \
  75          for i in xrange(nb_cores) ]
  76
  77 # overwrite options.num_cpus with the nb_cores value
  78 options.num_cpus = nb_cores
  79
  80 # system simulated
  81 system = System(cpu = cpus)
  82 # Dummy voltage domain for all our clock domains
  83 system.voltage_domain = VoltageDomain()
  84 system.clk_domain = SrcClockDomain(clock = '1GHz',
  85                                    voltage_domain = system.voltage_domain)
  86
  87 # Create a seperate clock domain for components that should run at
  88 # CPUs frequency
  89 system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
  90                                        voltage_domain = system.voltage_domain)
  91
  92 # All cpus are associated with cpu_clk_domain
  93 for cpu in cpus:
  94     cpu.clk_domain = system.cpu_clk_domain
  95
  96 system.mem_ranges = AddrRange('256MB')
  97
  98 Ruby.create_system(options, False, system)
  99
 100 # Create a separate clock domain for Ruby
 101 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
 102                                         voltage_domain = system.voltage_domain)
 103
 104 assert(len(cpus) == len(system.ruby._cpu_ports))
 105
 106 for (i, ruby_port) in enumerate(system.ruby._cpu_ports):
 107      #
 108      # Tie the cpu port to the ruby cpu ports and
 109      # physmem, respectively
 110      #
 111      cpus[i].port = ruby_port.slave
 112
 113      #
 114      # Since the memtester is incredibly bursty, increase the deadlock
 115      # threshold to 1 million cycles
 116      #
 117      ruby_port.deadlock_threshold = 1000000
 118
 119 # -----------------------
 120 # run simulation
 121 # -----------------------
 122
 123 root = Root(full_system = False, system = system)
 124 root.system.mem_mode = 'timing'
 125
 126 # Not much point in this being higher than the L1 latency
 127 m5.ticks.setGlobalFrequency('1ns')