tests/configs/memtest-ruby.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # Copyright (c) 2010 Advanced Micro Devices, Inc.
   3 # All rights reserved.
   4 #
   5 # Redistribution and use in source and binary forms, with or without
   6 # modification, are permitted provided that the following conditions are
   7 # met: redistributions of source code must retain the above copyright
   8 # notice, this list of conditions and the following disclaimer;
   9 # redistributions in binary form must reproduce the above copyright
  10 # notice, this list of conditions and the following disclaimer in the
  11 # documentation and/or other materials provided with the distribution;
  12 # neither the name of the copyright holders nor the names of its
  13 # contributors may be used to endorse or promote products derived from
  14 # this software without specific prior written permission.
  15 #
  16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27 #
  28 # Authors: Ron Dreslinski
  29
  30 import m5
  31 from m5.objects import *
  32 from m5.defines import buildEnv
  33 from m5.util import addToPath
  34 import os, optparse, sys
  35
  36 # Get paths we might need
  37 config_path = os.path.dirname(os.path.abspath(__file__))
  38 config_root = os.path.dirname(config_path)
  39 m5_root = os.path.dirname(config_root)
  40 addToPath(config_root+'/configs/common')
  41 addToPath(config_root+'/configs/ruby')
  42 addToPath(config_root+'/configs/topologies')
  43
  44 import Ruby
  45 import Options
  46
  47 parser = optparse.OptionParser()
  48 Options.addCommonOptions(parser)
  49
  50 # Add the ruby specific and protocol specific options
  51 Ruby.define_options(parser)
  52
  53 (options, args) = parser.parse_args()
  54
  55 #
  56 # Set the default cache size and associativity to be very small to encourage
  57 # races between requests and writebacks.
  58 #
  59 options.l1d_size="256B"
  60 options.l1i_size="256B"
  61 options.l2_size="512B"
  62 options.l3_size="1kB"
  63 options.l1d_assoc=2
  64 options.l1i_assoc=2
  65 options.l2_assoc=2
  66 options.l3_assoc=2
  67 options.ports=32
  68
  69 #MAX CORES IS 8 with the fals sharing method
  70 nb_cores = 8
  71
  72 # ruby does not support atomic, functional, or uncacheable accesses
  73 cpus = [ MemTest(atomic=False, percent_functional=50,
  74                  percent_uncacheable=0, suppress_func_warnings=True) \
  75          for i in xrange(nb_cores) ]
  76
  77 # overwrite options.num_cpus with the nb_cores value
  78 options.num_cpus = nb_cores
  79
  80 # system simulated
  81 system = System(cpu = cpus,
  82                 funcmem = SimpleMemory(in_addr_map = False),
  83                 funcbus = NoncoherentXBar())
  84 # Dummy voltage domain for all our clock domains
  85 system.voltage_domain = VoltageDomain()
  86 system.clk_domain = SrcClockDomain(clock = '1GHz',
  87                                    voltage_domain = system.voltage_domain)
  88
  89 # Create a seperate clock domain for components that should run at
  90 # CPUs frequency
  91 system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
  92                                        voltage_domain = system.voltage_domain)
  93
  94 # All cpus are associated with cpu_clk_domain
  95 for cpu in cpus:
  96     cpu.clk_domain = system.cpu_clk_domain
  97
  98 system.mem_ranges = AddrRange('256MB')
  99
 100 Ruby.create_system(options, False, system)
 101
 102 # Create a separate clock domain for Ruby
 103 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
 104                                         voltage_domain = system.voltage_domain)
 105
 106 assert(len(cpus) == len(system.ruby._cpu_ports))
 107
 108 for (i, ruby_port) in enumerate(system.ruby._cpu_ports):
 109      #
 110      # Tie the cpu test and functional ports to the ruby cpu ports and
 111      # physmem, respectively
 112      #
 113      cpus[i].test = ruby_port.slave
 114      cpus[i].functional = system.funcbus.slave
 115
 116      #
 117      # Since the memtester is incredibly bursty, increase the deadlock
 118      # threshold to 1 million cycles
 119      #
 120      ruby_port.deadlock_threshold = 1000000
 121
 122 # connect reference memory to funcbus
 123 system.funcmem.port = system.funcbus.master
 124
 125 # -----------------------
 126 # run simulation
 127 # -----------------------
 128
 129 root = Root(full_system = False, system = system)
 130 root.system.mem_mode = 'timing'
 131
 132 # Not much point in this being higher than the L1 latency
 133 m5.ticks.setGlobalFrequency('1ns')